DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 56

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The Transmit FDL register (T1TFDL) contains the facility data link (FDL) information that is to be inserted on a byte
basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used.
8.9.5.4 Legacy T1 Receive FDL
It is recommended that the DS26528’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL.
Table 8-21. Registers Related to T1 Receive FDL
Receive FDL Register (T1RFDL)
Receive Latched Status Register 7(RLS7)
Receive Interrupt Mask Register 7(RIM7)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 8 for Framers 2 to 8.
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register
(T1RFDL). Since the
controller that the buffer has filled via the RLS7.2 bit. If enabled via RIM7.2, the INTB pin toggles low, indicating
that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note that no
zero destuffing is applied for the data provided through the
facility data link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode,
multiframe boundaries and reports only the Fs bits.
8.9.6 E1 Data Link
Table 8-22
Table 8-22. Registers Related to E1 Data Link
E1 Receive Align Frame Register (E1RAF)
E1 Receive Non-Align Frame Register
Register (E1RNAF)
E1 Received Si Bits of the Align Frame
Register (E1RSiAF)
Received Si Bits of the Non-Align Frame
Register E1RSiNAF)
Received Sa4 to Sa8 Bits Register
(E1RSa4
Transmit Align Frame Register (E1TAF)
Transmit Non-Align Frame Register
(E1TNAF)
Transmit Si Bits of the Align Frame
Register (E1TSiAF)
Transmit Si Bits of the Non-Align Frame
Register (E1TSiNAF)
Transmit Sa4 to Sa8 Bits Register
(E1TSa4
E1 Transmit Sa-Bit Control Register
(E1TSACR)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 8 for Framers 2 to 8.
to E1TSa8)
to E1RSa8)
shows the registers related to E1 data link.
REGISTER
REGISTER
Table 8-21
T1RFDL
shows the registers related to the receive FDL.
is 8 bits in length, it fills up every 2ms (8 x 250μs). The framer signals an external
ADDRESSES
06Bh, 06Ch,
16Bh, 16Ch,
069h, 06Ah,
169h, 16Ah,
FRAMER
ADDRESSES
06Dh
16Dh
064h
065h
066h
067h
164h
165h
166h
167h
114h
FRAMER
56 of 276
0A6h
062h
096h
T1RFDL
Receive frame alignment register.
Receive non-frame alignment register.
Receive Si bits of the frame alignment frames.
Receive Si bits of the non-frame alignment
frames.
Receive Sa bits.
Transmit align frame register.
Transmit non-align frame register.
Transmit Si bits of the frame alignment frames.
Transmit Si bits of the non-frame alignment
frames.
Transmit Sa4 to Sa8.
Transmit sources of Sa control.
register. The
FDL code used to insert transmit FDL.
Receive FDL full bit is in this register.
Mask bit for RFDL full.
DS26528 Octal T1/E1/J1 Transceiver
FUNCTION
T1RFDL
FUNCTION
reports the incoming
T1RFDL
updates on