DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 27

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.
8.1
Microprocessor control of the DS26528 is accomplished through the 28 hardware pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select
(BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in
When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in
address space is mapped through the use of 13 address lines, A[12:0]. Multiplexed mode is not supported on the
processor interface.
The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the
microprocessor port. With Intel timing selected, the read-data bar (RDB) and write-read bar (WRB) pins are used to
indicate read and write operations and latch data through the interface. With Motorola timing selected, the read-
write bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to
latch data through the interface.
The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The device has
a bulk write mode that allows a microprocessor to write all eight internal transceivers with each bus write cycle. By
setting the BWE bit (GTCR1.2), each port write cycle will write to all four framers, LIUs, or BERTs at the same time.
The BWE bit must be cleared before normal write operation is resumed. This function is useful for device
initialization. The register map is shown in
8.2
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1
and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.
8.2.1 Backplane Clock Generation
The DS26528 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see
Figure
generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can output MCLKT1
or MCLKE1 as shown in
This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26528 and other IBO-equipped devices
as an IBO bus master. Hence, the DS26528 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz clock.
This can be used by the link layer devices and frames connected to the IBO bus.
Processor Interface
8-1). The Global Transceiver Clock Control register (GTCCR) is used to control the backplane clock
FUNCTIONAL DESCRIPTION
Clock Structure
Figure
8-1.
Figure
9-1.
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DS26528 Octal T1/E1/J1 Transceiver
Figure 12-3
Figure 12-1
and
Figure
and
Figure
12-4. The
12-2.