DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 163

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver. This bit is
active in ESF framing mode only, and will set only if an RAI condition is being detected (RRTS1.3). When the host
reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1
seconds).
Bit 4: Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver. This bit
will set only if an AIS condition is being detected (RRTS1.2). This is a latched bit that must be cleared by the host,
and will set again each time the AIS-CI pattern is detected (approximately every 1.2 seconds).
Bit 3: Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the
Fs-bit stream, and the RSLCx registers have data available for retrieval. See Section
Bit 2: Receive FDL Register Full Event (RFDLF). Set when the 8-bit
operation, or manual extraction of FDL data bits. See Section
Bit 1: BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the disintegration filter applied).
Bit 0: BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 1: Sa6 Codeword Detect (Sa6CD). Set when a valid codeword (per ETS 300 233) is detected in the Sa6 bit
positions.
Bit 0: SaX Bit Change Detect (SaXCD). Set when a bit change is detected in the SaX bit position. The enabled
SaX bits are selected by the
—
—
7
0
7
0
RLS7 (T1 Mode)
Receive Latched Status Register 7
096h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RLS7 (E1 Mode)
Receive Latched Status Register 7
096h + (200h x n): where n = 0 to 7, for Ports 1 to 8
—
—
E1RSAIMR
6
0
6
0
RRAI-CI
register.
—
5
0
5
0
RAIS-CI
163 of 276
—
4
0
4
0
RLS7
RLS7
8.9.5.4
for E1 mode.
for T1 mode.
RSLC96
—
3
0
3
0
for more information.
T1RFDL
DS26528 Octal T1/E1/J1 Transceiver
RFDLF
—
2
0
2
0
register is full. Useful for SLC-96
8.9.4.5
Sa6CD
for more information.
BC
1
0
1
0
SaXCD
BD
0
0
0
0