DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 23

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RCHBLK/
RCHBLK/
RCHBLK/
RCHBLK/
RCHBLK/
RCHBLK/
RCHBLK/
RCHBLK/
BPCLK
NAME
LTC1
LTC2
LTC3
LTC4
LTC5
LTC6
LTC7
LTC8
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
RLF/
RLF/
RLF/
RLF/
RLF/
RLF/
RLF/
RLF/
M14
G13
N14
E14
D14
T11
T13
C12
PIN
M3
D3
E3
N3
E4
B5
E8
L6
T5
TYPE
O
O
O
Receive Loss of Frame/Loss of Transmit Clock. This pin can be programmed to
either toggle high when the synchronizer is searching for the frame and multiframe,
or to toggle high if the TCLK pin has not been toggled for approximately three clock
periods.
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a user-
programmable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK. RCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, RCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, RCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-to-
serial conversion of channel data. In either mode, RCHCLK is synchronous with
RCLKn when the receive-side elastic store is disabled or it is synchronous with
RSYSCLKn when the receive-side elastic store is enabled. The mode of
RCHCLKn is determined by the RGCLKEN bit in the RESCR register.
Backplane Clock. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
23 of 276
FUNCTION
DS26528 Octal T1/E1/J1 Transceiver