DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 264

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS26528 Octal T1/E1/J1 Transceiver
13.1
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
See
Figure
13-2.
13.1.1 Test-Logic-Reset
Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the IDCODE
instruction. All system logic of the device operates normally.
13.1.2 Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test
registers remain idle.
13.1.3 Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the
Capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller
to the Select-IR-Scan state.
13.1.4 Capture-DR
Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not
call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current
value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is LOW, or it goes to the
Exit1-DR state if JTMS is HIGH.
13.1.5 Shift-DR
The test data register selected by the current instruction is connected between JTDI and JTDO and shifts data one
stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is
not placed in the serial path, it maintains its previous state.
13.1.6 Exit1-DR
While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates the
scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-DR
state.
13.1.7 Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain
their previous state. The controller remains in this state while JTMS is LOW. A rising edge on JTCLK with JTMS
HIGH puts the controller in the Exit2-DR state.
13.1.8 Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state and
terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state.
13.1.9 Update-DR
A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
13.1.10 Select-IR-Scan
All test registers retain their previous state. The instruction register remains unchanged during this state. With
JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence
for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-
Reset state.
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