DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 61

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially
interleaving 0.99 seconds of “00000000 11111111” (right-to-left ) with 90ms of “00111110 11111111.” The RRAI-CI
bit is set when a bit-oriented code of “00111110 11111111” is detected while RRAI (RRTS1.3) is set. The RRAI-CI
detector uses the receive BOC filter bits (RBF0 and RBF1) located in RBOCC to determine the integration time for
RAI-CI detection. Like RAIS-CI, the RRAI-CI bit is latched and should be cleared by the host when read.
RRAI-CI continues to set approximately every 1.1 seconds that the condition is present. The host needs to poll the
bit in conjunction with the normal RAI indicators to determine when the condition has cleared. It may be useful to
enable the 200ms ESF RAI integration time with the RAIIE control bit (T1RCR2.1) in networks that use RAI-CI.
8.9.8.2 T1 Receive-Side Digital Milliwatt Code Generation
Receive-side digital milliwatt code generation involves using the T1 Receive Digital Milliwatt registers
(T1RDMWE1:T1RDMWE3) to determine which of the 24 T1 channels of the T1 line going to the backplane should
be overwritten with a digital milliwatt pattern. The digital milliwatt code is an 8-byte repeating pattern that represents
a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMWE1, T1RDMWE2, and
registers represents a particular channel. If a bit is set to 1, the receive data in that channel is replaced with the
digital milliwatt code. If a bit is set to 0, no replacement occurs.
8.9.9 Error-Count Registers
The DS26528 contains four counters that are used to accumulate line coding errors, path errors, and
synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1
mode only), or manually. See the Error-Counter Configuration register (ERCNT). When updated automatically, the
user can use the interrupt from the timer to determine when to read these registers. All four counters saturate at
their respective maximum counts and they will not roll over. (Note: Only the Line Code Violation Count register has
the potential to overflow, but the bit error would have to exceed 10E-2 before this would occur.)
The DS26528 can share the one-second timer from Port 1 across all ports. All DS26528 error/performance
counters can be configured to update on the shared one-second source, or a separate manual update signal input.
See the Error-Counter Configuration register
cores to synchronously latch their counters, the host software can be streamlined to read and process performance
information from multiple spans in a more controlled manner.
8.9.9.1 Line Code Violation Count Register (LCVCR)
Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of
the same polarity. In T1 mode, if the B8ZS mode is set for the receive side, then B8ZS codewords are not counted
as BPVs. In E1 mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as
BPVs. If ERCNT.0 is set, then the LCVCR counts code violations as defined in ITU-T O.161. Code violations are
defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be
programmed to count BPVs when receiving AMI code and to count CVs when receiving B8ZS or HDB3 code. This
counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and
will not rollover. The bit-error rate on an E1 line would have to be greater than 10E-2 before the PCVCR would
saturate. See
Table 8-25. T1 Line Code Violation Counting Options
COUNT EXCESSIVE
(ERCNT.0)
ZEROS?
Yes
Yes
No
No
Table 8-25
and
Table 8-26
B8ZS ENABLED?
(RCR1.6)
Yes
Yes
No
No
for details of exactly what the LCVCRs count.
ERCNT
61 of 276
register for more information. By allowing multiple framer
BPVs (B8ZS/HDB3 codewords not counted)
BPVs + 16 consecutive zeros
BPVs + 8 consecutive zeros
WHAT IS COUNTED IN
LCVCR1,
DS26528 Octal T1/E1/J1 Transceiver
BPVs
LCVCR2
T1RDMWE3