DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 184

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used.
Bit 6: Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used.
Bit 5: Transmit Bit 6 Suppress (TBSE6). Set to one to stop this bit from being used.
Bit 4: Transmit Bit 5 Suppress (TBSE5). Set to one to stop this bit from being used.
Bit 3: Transmit Bit 4 Suppress (TBSE4). Set to one to stop this bit from being used.
Bit 2: Transmit Bit 3 Suppress (TBSE3). Set to one to stop this bit from being used.
Bit 1: Transmit Bit 2 Suppress (TBSE2). Set to one to stop this bit from being used.
Bit 0: Transmit Bit 1 Suppress (TBSE1). LSB of the channel. Set to one to stop this bit from being used.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Abort (TABT). A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to
be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be
cleared and set again for a subsequent abort to be sent.
Bit 6: Send BOC (SBOC) (T1 Mode Only). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the
register.
Bit 5: Transmit HDLC Controller Enable (THCEN).
Bits 4 to 0: Transmit HDLC Channel Select (THCS[4:0]). Determines which DSO channel will carry the HDLC
message if enabled. Changes to this value are acknowledged only upon a transmit HDLC controller reset (THR at
THC1.5).
0 = Transmit HDLC controller is not enabled.
1 = Transmit HDLC controller is enabled.
TBSE8
TABT
TABT
7
0
7
0
THBSE
Transmit HDLC Bit Suppress Register
111h + (200h x n): where n = 0 to 7, for Ports 1 to 8
THC2
Transmit HDLC Control Register 2
113h + (200h x n): where n = 0 to 7, for Ports 1 to 8
TBSE7
SBOC
—
6
0
6
0
THCEN
THCEN
TBSE6
5
0
5
0
THCS4
THCS4
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TBSE5
4
0
4
0
THCS3
TBSE4
THCS3
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
THCS2
THCS2
TBSE3
2
0
2
0
THCS1
TBSE2
THCS1
1
0
1
0
T1TBOC
THCS0
THCS0
TBSE1
0
0
0
0