DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 213

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real time.
Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 1: Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties
beyond the low watermark as defined by the transmit low watermark bits (TLWM).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte
available.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 6 to 0: Transmit FIFO Bytes Available (TFBA[6:0]). TFBA0 is the LSB.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte.
Bit 6: Transmit HDLC Data Bit 6 (THD6).
Bit 5: Transmit HDLC Data Bit 5 (THD5).
Bit 4: Transmit HDLC Data Bit 4 (THD4).
Bit 3: Transmit HDLC Data Bit 3 (THD3).
Bit 2: Transmit HDLC Data Bit 2 (THD2).
Bit 1: Transmit HDLC Data Bit 1 (THD1).
Bit 0: Transmit HDLC Data Bit 0 (THD0). LSB of an HDLC packet data byte.
THD7
—
—
7
0
7
0
7
0
TRTS2
Transmit Real-Time Status Register 2 (HDLC)
1B1h + (200h x n): where n = 0 to 7, for Ports 1 to 8
TFBA
Transmit HDLC FIFO Buffer Available
1B3h + (200h x n): where n = 0 to 7, for Ports 1 to 8
THF
Transmit HDLC FIFO Register
1B4h + (200h x n): where n = 0 to 7, for Ports 1 to 8
TFBA6
THD6
—
6
0
6
0
6
0
TFBA5
THD5
—
5
0
5
0
5
0
213 of 276
TFBA4
THD4
—
4
0
4
0
4
0
TEMPTY
TFBA3
THD3
3
0
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
TFBA2
TFULL
THD2
2
0
2
0
2
0
TFBA1
TLWM
THD1
1
0
1
0
1
0
TFBA0
THD0
TNF
0
0
0
0
0
0