C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 124

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 13.1 for a block diagram).
The CIP-51 includes the following features:
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
124
Number of Instructions
Clocks to Execute
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
26
PSW
PRGM. ADDRESS REG.
LOGIC
1
POWER CONTROL
PC INCREMENTER
Figure 13.1. CIP-51 Block Diagram
DATA POINTER
REGISTER
BUFFER
50
2
TMP1
PIPELINE
ALU
2/3
Rev. 1.2
5
TMP2
DATA BUS
DATA BUS
D8
D8
D8
14
3
A16
D8
D8
D8
D8
B REGISTER
REGISTER
ADDRESS
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
MEMORY
SRAM
SFR
BUS
3/4
7
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
4
3
SRAM
MEM_CONTROL
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
DEBUG_IRQ
4/5
1
5
2
8
1