C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 163

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

14.
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the exter-
nal I/O pins to a high state. The external I/O pins do not go high immediately, but will go high within four
system clock cycles after entering the reset state. This allows power to be conserved while the part is held
in reset. For VDD Monitor resets, the /RST pin is driven low until the end of the VDD reset timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator running at its lowest frequency. Refer to Section
on selecting and configuring the system clock source. The Watchdog Timer is enabled using its longest
timeout interval (see Section
is stable, program execution begins at location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on, power-fail, external /RST pin,
external CNVSTR2 signal, software command, Comparator0, Missing Clock Detector, and Watchdog
Timer. Each reset source is described in the following sections.
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External port pins are forced to a known configuration
Interrupts and timers are disabled.
Reset Sources
(Port
XTAL1
XTAL2
I/O)
CP0+
CP0-
Generator
Internal
Clock
Crossbar
OSC
“14.7. Watchdog Timer
Comparator0
CNVSTR2
+
-
(CNVSTR
enable)
reset
enable)
(CP0
reset
Clock Select
System
Clock
Figure 14.1. Reset Sources
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Rev. 1.2
Extended Interrupt
CIP-51
VDD
Core
Handler
Reset” on page 165). Once the system clock source
C8051F060/1/2/3/4/5/6/7
EN
WDT
PRE
Supply
Monitor
+
-
“15.
Software Reset
System Reset
VDD Monitor
reset enable
Oscillators” on page
Timeout
Supply
Reset
(wired-OR)
(wired-OR)
Reset
Funnel
171
for information
/RST
163