ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 120
Manufacturer Part Number
MCU AVR 32K FLASH 32TQFP
Specifications of ATMEGA328P-AU
I²C, SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
32KB (16K x 16)
Program Memory Type
1K x 8
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
Data Bus Width
Data Ram Size
2-Wire, SPI, USART
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
10 bit, 8 Channel
Device Core Size
Total Internal Ram Size
# I/os (max)
Number Of Timers - General Purpose
Operating Supply Voltage (typ)
Operating Supply Voltage (max)
Operating Supply Voltage (min)
Instruction Set Architecture
Operating Temp Range
-40C to 85C
Operating Temperature Classification
No. Of I/o's
Eeprom Memory Size
Ram Memory Size
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ATMEGA328P-AU - MCU
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT1H value when the TCNT1L is read, and
TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OC1x. For more details about advanced counting
sequences and waveform generation, see
shows a block diagram of the counter and its surroundings.
is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTn (16-bit Counter)
). The clk
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
can be generated from an external or internal clock source,
”Modes of Operation” on page
( From Prescaler )