ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 330

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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8271C–AVR–08/10
Figure 28-6. Parallel Programming Timing, Including some General Timing Requirements
Figure 28-7. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 28-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
XTAL1
DATA
(DATA, XA0/1, BS1, BS2)
BS1
XA0
XA1
OE
PAGEL
XTAL1
1. The timing requirements shown in
1. The timing requirements shown in
DATA
BS1
XA0
XA1
ing operation.
ing operation.
Data & Contol
Timing Requirements
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
(LOW BYTE)
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
WR
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 28-6
Figure 28-6
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
t
BVDV
(i.e., t
(i.e., t
t
(HIGH BYTE)
BVWL
LOAD DATA
DATA (High Byte)
DVXH
DVXH
(HIGH BYTE)
READ DATA
t
t
DATA (High Byte)
XLPH
WLWH
WLRL
LOAD DATA
, t
, t
XHXL
XHXL
, and t
, and t
t
PLXH
t
OHDZ
t
WLBX
XLDX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
ADDR1 (Low Byte)
) also apply to read-
) also apply to load-
ADDR1 (Low Byte)
t
WLRH
(1)
330

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