ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 65

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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8271C–AVR–08/10
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in ATmega168A/168PA is:
When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega168A/168PA is:
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATmega168A/168PA is:
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
0x0034
0x0035
0x0036
0x0037
0x0038
Address Labels Code
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
;
.org 0x1C02
0x1C02
0x1C04
...
0x1C32
Address Labels Code
.org 0x0002
0x0002
0x0004
...
0x0032
;
.org 0x1C00
0x1C00
0x1C01
0x1C02
0x1C03
0x1C04
0x1C05
...
RESET: ldi
RESET: ldi
...
out
ldi
out
sei
<instr>
out
ldi
out
sei
<instr>
jmp
jmp
...
jmp
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
...
...
SPH,r16
r16, low(RAMEND)
SPL,r16
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
EXT_INT0
EXT_INT1
...
SPM_RDY
EXT_INT0
EXT_INT1
...
SPM_RDY
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
xxx
xxx
Comments
; Set Stack Pointer to top of RAM
; Enable interrupts
Comments
; Set Stack Pointer to top of RAM
; Enable interrupts
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
65

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