ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 93

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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13.4
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
8271C–AVR–08/10
Register Description
MCUCR – MCU Control Register
PORTB – The Port B Data Register
DDRB – The Port B Data Direction Register
PINB – The Port B Input Pins Address
PORTC – The Port C Data Register
DDRC – The Port C Data Direction Register
PINC – The Port C Input Pins Address
Notes:
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 77
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x05 (0x25)
Read/Write
Initial Value
Bit
0x04 (0x24)
Read/Write
Initial Value
Bit
0x03 (0x23)
Read/Write
Initial Value
Bit
0x08 (0x28)
Read/Write
Initial Value
Bit
0x07 (0x27)
Read/Write
Initial Value
Bit
0x06 (0x26)
Read/Write
Initial Value
1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P
PORTB7
PINB7
DDB7
R/W
R/W
N/A
R
7
0
R
R
R
R
7
0
7
0
7
7
0
7
0
7
0
PORTB6
PORTC6
BODS
PINB6
PINC6
DDB6
DDC6
R/W
R/W
R/W
R/W
R/W
N/A
N/A
R
R
6
0
6
0
6
6
0
6
0
6
6
0
(1)
for more details about this feature.
PORTB5
PORTC5
BODSE
PINB5
PINC5
DDB5
DDC5
R/W
R/W
R/W
R/W
N/A
N/A
R/W
R
R
5
0
5
0
5
5
0
5
0
5
5
0
(1)
PORTB4
PORTC4
PINB4
PINC4
DDB4
DDC4
R/W
R/W
R/W
R/W
N/A
N/A
R
R
4
0
4
0
4
4
0
4
0
4
PUD
R/W
4
0
PORTB3
PORTC3
PINB3
PINC3
DDB3
DDC3
R/W
R/W
R/W
R/W
N/A
N/A
R
R
3
0
3
0
3
3
0
3
0
3
R
3
0
PORTB2
PORTC2
PINB2
PINC2
DDB2
DDC2
R/W
R/W
R/W
R/W
N/A
N/A
R
R
2
0
2
0
2
2
0
2
0
2
R
2
0
PORTB1
PORTC1
PINB1
PINC1
DDB1
DDC1
IVSEL
R/W
R/W
R/W
R/W
N/A
N/A
R/W
R
R
1
0
1
0
1
1
0
1
0
1
1
0
PORTB0
PORTC0
PINB0
PINC0
DDB0
DDC0
IVCE
R/W
R/W
R/W
R/W
R/W
N/A
N/A
R
R
0
0
0
0
0
0
0
0
0
0
0
0
MCUCR
PORTB
PORTC
DDRB
DDRC
PINB
PINC
”Con-
93

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