ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 101

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
Note:
Note:
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
–
–
An access to the SPICSR register while the SPIF bit is set.
A read to the SPIDR register.
Write to the SPICSR register to perform the following actions:
–
–
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
–
–
An access to the SPICSR register while the SPIF bit is set.
A write or a read to the SPIDR register.
The SPIF bit is set by hardware
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see
master.
Manage the SS pin as described in
Figure
be held low during byte transmission and pulled up between each byte to let the
slave write in the shift register.
The SPIF bit is set by hardware
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Figure
50. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must
52). The slave must have the same CPOL and CPHA settings as the
Doc ID13466 Rev 4
Slave Select management on page 99
On-chip peripherals
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and