ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 48

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

Interrupts
7.6
7.6.1
48/198
External interrupts
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register
sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
●
●
●
●
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
Figure 20. External interrupt control bits
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
(Figure
PF2
PB4
PA3
PB3
Port F [2:0] interrupts
Port B4 interrupt
Port A3 interrupt
Port B [3:0] interrupts
PFDDR.2
PBDDR.4
PADDR.3
PBDDR.3
PFOR.2
PBOR.4
PAOR.3
PBOR.3
20). This control allows up to four fully independent external interrupt source
IPA BIT
IPB BIT
Doc ID13466 Rev 4
IS20
IS10
IS20
IS10
Sensitivity
Sensitivity
Sensitivity
Sensitivity
control
control
control
EICR
EICR
control
EICR
EICR
IS21
IS11
IS21
IS11
PF2
PF1
PF0
PB3
PB2
PB1
PB0
ei1 interrupt source
ei3 interrupt source
ei0 interrupt source
ei2 interrupt source
ST72324B-Auto