ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 69

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
10.1.9
10.2
10.2.1
Control register (WDGCR)
Table 35.
Table 36.
Main clock controller with real-time clock and beeper
(MCC/RTC)
The main clock controller consists of three different functions:
●
●
●
Each function can be used independently and simultaneously.
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power saving mode (see
for more details).
The prescaler selects the f
MCCSR register: CP[1:0] and SMS.
WDGCR
Address (Hex.) Register label
Bit
6:0
7
WDGA
R/W
a programmable CPU clock prescaler
a clock-out signal to supply external devices
a real-time clock timer with interrupt capability
7
002Ah
WDGA
Name
T[6:0]
WDGCR register description
Watchdog timer register map and reset values
Activation bit
7-bit counter (MSB to LSB)
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
These bits contain the value of the Watchdog counter, which is decremented every
16384 f
(T6 is cleared).
6
WDGCR
reset value
OSC2
CPU
cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh
5
Doc ID13466 Rev 4
main clock frequency and is controlled by three bits in the
WDGA
7
0
4
T6
6
1
Function
T[6:0]
T5
R/W
5
1
3
Section 8.2: Slow mode on page 52
T4
4
1
2
Reset value: 0111 1111 (7F h)
T3
3
1
On-chip peripherals
T2
2
1
1
T1
1
1
0
69/198
T0
0
1