ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 169

IC MCU 8BIT 32K FLASH 44-LQFP

ST72F324BJ6T6

Manufacturer Part Number
ST72F324BJ6T6
Description
IC MCU 8BIT 32K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F324BJ6T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-5590

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ST72324B-Auto
12.12
12.12.1
Table 110. SPI characteristics
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on f
t
t
w(SCKH)
t
w(SCKL)
1/t
t
Symbol
t
t
t
t
t
dis(SO)
t
t
t
su(SS)
t
t
su(MI)
v(MO)
h(MO)
h(SS)
su(SI)
a(SO)
v(SO)
h(SO)
t
t
h(MI)
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Communication interface characteristics
Serial peripheral interface (SPI)
The following characteristics are ubject to general operating conditions for V
unless otherwise specified. The data is based on design simulation and/or characterization
results, not tested in production.
When no communication is on-going the data output line of the SPI (MOSI in master mode,
MISO in slave mode) has its alternate function capability released. In this case, the pin
status depends on the I/O port configuration. Refer to the I/O port characteristics for more
details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
CPU
. For example, if f
Parameter
(2)
CPU
= 8 MHz, then t
Master f
Slave f
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
CPU
Conditions
Doc ID13466 Rev 4
CPU
= 8 MHz
CPU
= 8 MHz
= 1 / f
CPU
= 125ns and t
f
CPU
/128 = 0.0625
t
CPU
Min
120
100
100
100
100
100
90
0
0
0
0
su(SS)
see I/O port pin description
+ 50
= 175ns.
Electrical characteristics
f
f
CPU
CPU
Max
120
240
120
120
DD
/4 = 2
/2 = 4
, f
CPU
, and T
169/198
Unit
MHz
ns
A

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