ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 127

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
SCI Data Register (SCIDR)
This register contains the received or transmitted data character, depending on whether it is
read from or written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
input shift register and the internal bus (see
SCI Baud Rate Register (SCIBRR)
Table 65.
SCIDR
SCIBRR
7:6 SCP[1:0]
Bit
DR7
R/W
7
7
Name
SCP[1:0]
R/W
SCIBRR register description
DR6
R/W
First SCI Prescaler
6
6
These 2 prescaling bits allow several standard clock division ranges.
00: PR prescaling factor = 1
01: PR prescaling factor = 3
10: PR prescaling factor = 4
11: PR prescaling factor = 13
Figure
55). The RDR register provides the parallel interface between the
DR5
R/W
5
5
Doc ID13466 Rev 4
SCT[2:0]
DR4
R/W
R/W
4
4
Figure
Function
DR3
R/W
3
3
55).
DR2
R/W
2
2
Reset value: 0000 0000 (00h)
Reset value: undefined
On-chip peripherals
SCR[2:0]
DR1
R/W
R/W
1
1
DR0
R/W
127/198
0
0