ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 105

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
10.4.6
Note:
Caution:
10.4.7
Low power modes
Table 53.
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. Therefore,
if Slave selection is configured as external (see
make sure the master drives a low level on the SS pin when the slave enters Halt mode.
Interrupts
Table 54.
1. The SPI interrupt events are connected to the same interrupt vector (see
SPI end of transfer event
Master mode fault event
Overrun error
Mode
Wait
Halt
generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC
register is reset (RIM instruction).
Interrupt event
No effect on SPI. 
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen. 
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an
interrupt with Exit from Halt mode capability. The data received is subsequently read from
the SPIDR register when the software is running (interrupt vector fetching). If several data
are received before the wake-up event, then an overrun error is generated. This error can
be detected after the fetch of the interrupt routine that woke up the device.
Effect of low power modes on SPI
SPI interrupt control/wake-up capability
Event flag
MODF
SPIF
OVR
Doc ID13466 Rev 4
Enable control bit
Description
SPIE
Slave Select management on page
(1)
Exit from WAIT Exit from HALT
Section 7:
Yes
On-chip peripherals
Interrupts). They
Yes
No
99),
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