ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 81

IC MCU 8BIT 32K FLASH 44-LQFP

ST72F324BJ6T6

Manufacturer Part Number
ST72F324BJ6T6
Description
IC MCU 8BIT 32K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F324BJ6T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-5590

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ST72324B-Auto
Output compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the Output Compare register and the free running counter,
the output compare function:
Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
Table 45.
These registers are readable and witable and are not affected by the timer hardware. A
reset event changes the OC
Timing resolution is one count of the free running counter: (f
Procedure
To use the Output Compare function, select the following in the CR2 register:
And select the following in the CR1 register:
When a match is found between OCRi register and CR register:
The OC
the following formula:
Where:
t
f
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see
CPU
Assigns pins with a programmable value if the OCiE bit is set
Sets a flag in the status register
Generates an interrupt if enabled
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
Select the timer clock (CC[1:0]) (see
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
Set the OCIE bit to generate an interrupt if it is needed.
OCFi bit is set
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
i
R register value required for a specific timing application can be calculated using
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Register
Output compare byte distribution
OCiR
i
R value to 8000h.
Doc ID13466 Rev 4
 OCiR =
Table
MS byte
OCiHR
t
PRESC
*
f
50).
CPU
CPU
/CC[1:0]).
On-chip peripherals
LS byte
OCiLR
Table
50)
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