ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 108

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

On-chip peripherals
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Table 57.
Bit
7
6
5
4
3
2
1
0
WCOL
MODF
Name
SPIF
OVR
SOD
SSM
SSI
-
SPICSR register description
Serial Peripheral data transfer flag
Write Collision status
SPI Overrun error
Mode Fault flag
Reserved, must be kept cleared.
SPI Output Disable
SS Management
SS Internal mode
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see
0: No write collision occurred
1: A write collision has been detected.
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see
condition (OVR) on page
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault (MODF) on page
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
0: No master mode fault detected
1: A fault in master mode has been detected.
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1).
1: SPI output disabled.
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See
on page
0: Hardware management (SS managed by external pin).
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O).
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS slave select signal when the SSM bit is set. 
0: Slave selected.
1: Slave deselected.
99.
Doc ID13466 Rev 4
103). An interrupt is generated if SPIE = 1 in SPICR
Function
103). An SPI interrupt can be generated if
Slave Select management
Figure
ST72324B-Auto
53).
Overrun