MC9S08AC16CFJE Freescale Semiconductor, MC9S08AC16CFJE Datasheet

IC MCU 8BIT 16K FLASH 32-LQFP

MC9S08AC16CFJE

Manufacturer Part Number
MC9S08AC16CFJE
Description
IC MCU 8BIT 16K FLASH 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of MC9S08AC16CFJE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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MC9S08AC16
MC9S08AC8
MC9S08AW16A
MC9S08AW8A
Data Sheet
HCS08
Microcontrollers
MC9S08AC16
Rev. 8
11/2009
freescale.com

Related parts for MC9S08AC16CFJE

MC9S08AC16CFJE Summary of contents

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MC9S08AC16 MC9S08AC8 MC9S08AW16A MC9S08AW8A Data Sheet HCS08 Microcontrollers MC9S08AC16 Rev. 8 11/2009 freescale.com ...

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MC9S08AC16 Series Features MC9S08AC16 Series Devices • Consumer & Industrial — MC9S08AC16 — MC9S08AC8 • Automotive — MC9S08AW16A — MC9S08AW8A 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • 20-MHz internal bus frequency • HC08 ...

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MC9S08AC16 Series Data Sheet Covers MC9S08AC16 MC9S08AC8 MC9S08AW16A MC9S08AW8A MC9S08AC16 Rev. 8 11/2009 ...

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... Updated the TPM 1 channel to 4 for the 32-pin packages in the Updated the bit 2 of IRQSC register in the Updated the Temp Sensor Voltage in the This product incorporates SuperFlash Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. 6 Description of Changes Table 4-2 ...

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... Serial Peripheral Interface (S08SPIV3) ................................ 209 Chapter 13 Inter-Integrated Circuit (S08IICV2) ....................................... 225 Chapter 14 Analog-to-Digital Converter (S08ADC10V1)........................ 243 Chapter 15 Development Support ........................................................... 271 Appendix A Electrical Characteristics and Timing Specifications ....... 293 Appendix B Ordering Information and Mechanical Drawings............... 319 Freescale Semiconductor List of Chapters Title MC9S08AC16 Series Data Sheet, Rev. 8 Page 7 ...

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... Stop3 Mode .......................................................................................................................38 3.6.3 Active BDM Enabled in Stop Mode .................................................................................38 3.6.4 LVD Enabled in Stop Mode ..............................................................................................39 3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................39 4.1 MC9S08AC16 Series Memory Map ...............................................................................................41 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42 Freescale Semiconductor Contents Title Chapter 1 Introduction Chapter 2 Pins and Connections ...

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... Interrupt Pin Request Status and Control Register (IRQSC) ............................................71 5.9.2 System Reset Status Register (SRS) .................................................................................72 5.9.3 System Background Debug Force Reset Register (SBDFR) ............................................73 5.9.4 System Options Register (SOPT) .....................................................................................74 5.9.5 System MCLK Control Register (SMCLK) .....................................................................75 10 Title Chapter 5 MC9S08AC16 Series Data Sheet, Rev. 8 Page Freescale Semiconductor ...

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... Port F I/O Registers (PTFD and PTFDD) .......................................................................102 6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) .................................................103 6.7.13 Port G I/O Registers (PTGD and PTGDD) .....................................................................104 6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ..............................................105 Freescale Semiconductor Title Chapter 6 Parallel Input/Output MC9S08AC16 Series Data Sheet, Rev. 8 ...

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... ICG Control Register 1 (ICGC1) ....................................................................................133 8.3.2 ICG Control Register 2 (ICGC2) ....................................................................................134 8.3.3 ICG Status Register 1 (ICGS1) .......................................................................................135 8.3.4 ICG Status Register 2 (ICGS2) .......................................................................................136 8.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................136 12 Title Chapter 7 Chapter 8 MC9S08AC16 Series Data Sheet, Rev. 8 Page Freescale Semiconductor ...

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... KBI Interrupt Controls ....................................................................................................158 10.1 Introduction ...................................................................................................................................159 10.2 Features .........................................................................................................................................159 10.3 TPMV3 Differences from Previous Versions ................................................................................161 10.3.1 Migrating from TPMV1 ..................................................................................................163 10.3.2 Features ...........................................................................................................................164 Freescale Semiconductor Title Chapter 9 Keyboard Interrupt (S08KBIV1) Chapter 10 Timer/PWM (S08TPMV3) MC9S08AC16 Series Data Sheet, Rev. 8 ...

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... SCI Data Register (SCIxD) .............................................................................................201 11.3 Functional Description ..................................................................................................................201 11.3.1 Baud Rate Generation .....................................................................................................201 11.3.2 Transmitter Functional Description ................................................................................202 11.3.3 Receiver Functional Description ....................................................................................203 11.3.4 Interrupts and Status Flags ..............................................................................................205 11.3.5 Additional SCI Functions ...............................................................................................206 14 Title Chapter 11 MC9S08AC16 Series Data Sheet, Rev. 8 Page Freescale Semiconductor ...

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... IIC Control Register (IIC1C1) ........................................................................................232 13.3.4 IIC Status Register (IIC1S) .............................................................................................232 13.3.5 IIC Data I/O Register (IIC1D) ........................................................................................233 13.3.6 IIC Control Register 2 (IIC1C2) .....................................................................................234 13.4 Functional Description ..................................................................................................................235 13.4.1 IIC Protocol .....................................................................................................................235 Freescale Semiconductor Title Chapter 12 Chapter 13 MC9S08AC16 Series Data Sheet, Rev. 8 Page ...

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... Input Select and Pin Control ...........................................................................................259 14.5.3 Hardware Trigger ............................................................................................................259 14.5.4 Conversion Control .........................................................................................................259 14.5.5 Automatic Compare Function .........................................................................................262 14.5.6 MCU Wait Mode Operation ............................................................................................262 16 Title Chapter 14 ) ..................................................................................................249 DDAD ) .................................................................................................249 SSAD ) ...................................................................................249 REFH ) ....................................................................................249 REFL MC9S08AC16 Series Data Sheet, Rev. 8 Page Freescale Semiconductor ...

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... A.5 ESD Protection and Latch-Up Immunity .......................................................................................296 A.6 DC Characteristics..........................................................................................................................297 A.7 Supply Current Characteristics.......................................................................................................301 A.8 ADC Characteristics.......................................................................................................................304 A.9 Internal Clock Generation Module Characteristics ........................................................................307 A.9.1 ICG Frequency Specifications .........................................................................................308 A.10 AC Characteristics..........................................................................................................................311 Freescale Semiconductor Title Chapter 15 Development Support Appendix A MC9S08AC16 Series Data Sheet, Rev. 8 Page ...

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... A.11 SPI Characteristics .........................................................................................................................314 A.12 FLASH Specifications....................................................................................................................316 A.13 EMC Performance..........................................................................................................................317 Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................319 B.2 Orderable Part Numbering System ................................................................................................320 B.3 Mechanical Drawings.....................................................................................................................321 18 Title Appendix B MC9S08AC16 Series Data Sheet, Rev. 8 Page Freescale Semiconductor ...

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... The MC9S08AW16A and MC9S08AW8A devices are qualified for, and are intended to be used in, automotive applications. Table 1-1 summarizes the feature set available in the MCUs. Freescale Semiconductor NOTE MC9S08AC16 Series Data Sheet, Rev. 8 Table 1-1 for 19 ...

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... The block diagram shows the structure of the MC9S08AC16 Series MCU. 20 Table 1-1. Features by MCU and Package Consumer and Industrial “AC” Devices MC9S08AC16 16K 1024 yes no Automotive “AW” Devices MC9S08AW16A 16K 1024 yes MC9S08AC16 Series Data Sheet, Rev. 8 MC9S08AC8 8K 768 yes no MC9S08AW8A 8K 768 yes Freescale Semiconductor ...

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... IRQ does not have a clamp diode Pin contains integrated pullup device. 5. PTD3, PTD2, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Freescale Semiconductor 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) DEBUG ...

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... SCI1 SCI2 SPI1 ADC1 RAM FLASH ADC has min and max FLASH has frequency frequency requirements. requirements for program See the Electricals appendix and erase operation. and the ADC chapter. See the Electricals appendix. Figure 1-2 shows a simplified clock Freescale Semiconductor ...

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... ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. Can also be used as the ALTCLK input to the ADC module. Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Chapter 1 Introduction 23 ...

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... Chapter 1 Introduction 24 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

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... RESET 3 4 PTF0/TPM1CH2 PTF1/TPM1CH3 5 6 PTF4/TPM2CH0 PTF5/TPM2CH1 7 8 PTF6 PTE0/TxD1 9 10 PTE1/RxD1 PTE2/TPM1CH0 11 PTE3/TPM1CH1 12 Figure 2-1. MC9S08AC16 Series in 48-Pin QFN Package Freescale Semiconductor 48-Pin QFN MC9S08AC16 Series Data Sheet, Rev PTG3/KBIP3 35 PTD3/KBIP6/AD1P11 34 PTD2/KBIP5/AD1P10 V 33 SSAD V 32 DDAD 31 PTD1/AD1P9 30 PTD0/AD1P8 PTB3/AD1P3 29 28 ...

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... IRQ/TPMCLK 2 RESET 3 PTF0/TPM1CH2 4 PTF1/TPM1CH3 5 PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 PTE0/TxD1 8 PTE1/RxD1 9 PTE2/TPM1CH0 10 PTE3/TPM1CH1 11 12 Figure 2-2. MC9S08AC16 Series in 44-Pin LQFP Package 44-Pin LQFP MC9S08AC16 Series Data Sheet, Rev PTG3/KBIP3 33 32 PTD3/KBIP6/AD1P11 PTD2/KBIP5/AD1P10 SSAD 29 V DDAD 28 PTD1/AD1P9 PTD0/AD1P8 27 26 PTB3/AD1P3 PTB2/AD1P2 25 PTB1/TPM3CH1/AD1P1 24 PTB0/TPM3CH0/AD1P0 Freescale Semiconductor ...

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... SDIP pin assignments for the MC9S08AC16 Series device. PTC0/SCL1 PTC1/SDA1 PTC2/MCLK PTC3/TxD2 PTC5/RxD2 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTE7/SPSCK1 V Figure 2-3. MC9S08AC16 Series in 42-Pin SDIP Package Freescale Semiconductor 42-Pin SDIP ...

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... LQFP pin assignments for the MC9S08AC16 Series device. IRQ/TPMCLK 1 RESET PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 Figure 2-4. MC9S08AC16 Series in 32-Pin LQFP Package 32-Pin LQFP MC9S08AC16 Series Data Sheet, Rev. 8 PTD3/AD1P11/KBIP6 24 PTD2/AD1P10/KBIP5 V SSAD V DDAD PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 Freescale Semiconductor ...

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... Keyboard interrupts KBIPx Timer/PWM TCLK, TPMCHx Inter-integrated circuit SCL, SDA Serial communications interface TxD, RxD Oscillator/clocking EXTAL, XTAL Analog-to-digital ADPx Power/core BKGD/MS, V Reset and interrupts RESET, IRQ Freescale Semiconductor Pin Number --> Highest Alt 1 Alt 2 25 — PTB0 TPMCLK PTB1 RESET PTB2 PTB3 ...

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... Chapter 2 Pins and Connections 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08AC16 Series application systems. 30 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

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... INPUT PTG0/KBIP0 PTG1/KBIP1 PTG2/KBIP2 PTG3/KBIP3 PTG4/KBIP4 PTG6/EXTAL NOTES: 1. Not required if using the internal clock option. 2. XTAL and EXTAL are PTG5 and PTG6 respectively filters on RESET and IRQ are recommended for EMC-sensitive applications. Freescale Semiconductor V REFH MC9S08AC16 V DDAD C BYAD 0.1 μF V SSAD ...

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... RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make DDAD SSAD (S08ICGV4).” (when used) and R S MC9S08AC16 Series Data Sheet, Rev. 8 and pin. This SS pin through a low-impedance SS ) equivalent to Self_reset should be low-inductance F Freescale Semiconductor ...

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... The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin does not perform any function. In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See an example. Freescale Semiconductor , V ) REFH REFL MC9S08AC16 Series Data Sheet, Rev ...

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... It is recommended that all modules that share a pin be disabled before enabling another module. 34 NOTE 2-2. Chapter 6, “Parallel NOTE Table 2-1 illustrates the priority if multiple MC9S08AC16 Series Data Sheet, Rev. 8 Chapter 6, “Parallel Input/Output” chapter for more details. Freescale Semiconductor ...

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... When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev ...

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... MCU is operated in run mode for the first time. When the MC9S08AC16 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...

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... To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...

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... ENBDM bit is set. After entering background debug mode, all background commands are available. Table 3-2 background debug mode is enabled. 38 Support” of this data sheet. If ENBDM is set when summarizes the behavior of the MCU in stop when entry into the MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

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... ICG is in standby by setting OSCSTEN. In stop2 mode, the ICG is turned off. The oscillator cannot be kept running in stop2 even if OSCSTEN is set. If the MCU is configured to go into stop2 mode, the ICG will be reset upon wake-up from stop and must be reinitialized. Freescale Semiconductor RAM ICG ...

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... If the MCU is configured to go into stop2 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters either of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. 40 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

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... BYTES 0x17FF 0x1800 HIGH PAGE REGISTERS 0x185F 0x1860 UNIMPLEMENTED 42,912 BYTES 0xBFFF 0xC000 16,384 BYTES 0xFFFF MC9S08AC16 and MC9S08AW16A Figure 4-1. MC9S08AC16 Series Memory Maps Freescale Semiconductor 0x0000 0x006F 0x0070 RAM 0x036F 0x0370 0x046F 0x0470 0x17FF 0x1800 0x185F 0x1860 0xBFFF ...

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... MC9S08AC16 Series Data Sheet, Rev. 8 Chapter 5, “Resets, Vector Name — Vtpm3ovf Vtpm3ch1 Vtpm3ch0 Vrti Viic1 Vadc1 Vkeyboard1 Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi1 Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf — — Vtpm1ch3 Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vswi Vreset Freescale Semiconductor ...

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... Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode which only and Table 4-4 the whole address in column one is shown in bold ...

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... KBACK KBIE KBIMOD KBIPE3 KBIPE2 KBIPE1 KBIPE0 CLKSA PS2 PS1 ELS0B ELS0A Freescale Semiconductor Bit 0 PTAD0 PTBD0 PTCD0 PTDD0 PTED0 PTFD0 PTGD0 — — R ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 — — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 ...

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... ICGC2 LOLRE 0x004A ICGS1 0x004B ICGS2 0 0x004C ICGFLTU 0 0x004D ICGFLTL 0x004E ICGTRM 0x004F Reserved — 0x0050 SPI1C1 SPIE 0x0051 SPI1C2 0 0x0052 SPI1BR 0 0x0053 SPI1S SPRF 0x0054 SPI1D Bit 7 Freescale Semiconductor CH1IE MS1B MS1A CH2IE MS2B MS2A CH3IE MS3B MS3A — — ...

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... ID11 ID10 ID9 ID3 ID2 ID1 0 RTIS2 RTIS1 RTIS0 1 LVDSE LVDE 0 BGBE PPDF PPDACK — PPDC — — — Freescale Semiconductor Bit 0 — — AD8 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — Bit 0 0 — ...

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... Bit 15 0x1837 TPM3C0VL Bit 7 0x1838 TPM3C1SC CH1F 0x1839 TPM3C1VH Bit 15 0x183A TPM3C1VL Bit 7 0x183B — Reserved 0x183F — 0x1840 PTAPE PTAPE7 0x1841 PTASE PTASE7 0x1842 PTADS PTADS7 0x1843 Reserved — Freescale Semiconductor — — — — — — — — — ...

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... R R PTFPE1 PTFPE0 R R PTFSE1 PTFSE0 R R PTFDS1 PTFDS0 — — — PTGPE3 PTGPE2 PTGPE1 PTGPE0 PTGSE3 PTGSE2 PTGSE1 PTGSE0 PTGDS3 PTGDS2 PTGDS1 PTGDS0 — — — — — — Freescale Semiconductor Bit 0 — — — — — — — ...

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... RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX #RamLast+1 TXS Freescale Semiconductor Table 4-4. Nonvolatile Register Summary 8-Byte Comparison Key — ...

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... FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 4.4.1 Features Features of the FLASH memory include: • ...

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... A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any unintended changes to the FLASH memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command. Freescale Semiconductor Table 4-5. Program and Erase Times Cycles of FCLK 9 ...

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... TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) YES FPVIOL OR FACCERR ? NO 0 FCCF ? 1 DONE MC9S08AC16 Series Data Sheet, Rev. 8 before checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...

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... FLASH BURST PROGRAM FLOW Figure 4-3. FLASH Burst Program Flowchart Freescale Semiconductor Note 1: Required only once after reset. (Note 1) WRITE TO FCDIV START ...

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... For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected 54 NVPROT)”). Figure 4-4. The FPS bits are used as the upper bits of the MC9S08AC16 Series Data Sheet, Rev. 8 Section 4.6.4, Freescale Semiconductor ...

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... FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state Freescale Semiconductor 1 A12 ...

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... Mass erase FLASH if necessary. 3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0. 56 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

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... Program/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5 μs to 6.7 μs. The automated programming logic uses an integer number of these pulses to complete an erase or program operation. See if PRDIV8 = 0 — PRDIV8 = 1 — f Table 4-7 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies. Freescale Semiconductor DIV5 DIV4 DIV3 ...

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... Table 4-8. FOPT Register Field Descriptions Description Section 4.5, MC9S08AC16 Series Data Sheet, Rev. 8 Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 5.2 μs 5 μs 5 μs 5 μs 5 μs 5 μs 5 μs 6.7 μ SEC01 “Security.” Table Freescale Semiconductor 0 SEC00 4-9. When ...

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... Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed KEYACC information about the backdoor key mechanism, refer to 0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command. 1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes. Freescale Semiconductor Table 4-9. Security States Description 0:0 0:1 ...

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... Writes to these bits have special meanings that are discussed in the bit descriptions FCCF FCBEF W Reset Unimplemented or Reserved FPS Description 5 4 FPVIOL FACCERR 0 0 Figure 4-9. FLASH Status Register (FSTAT) MC9S08AC16 Series Data Sheet, Rev FBLANK Freescale Semiconductor 0 1 FPDIS ...

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... Only five command codes are recognized in normal user modes as shown in Section 4.4.3, “Program and Erase Command programming and erase operations FCMD7 FCMD6 W Reset 0 0 Figure 4-10. FLASH Command Register (FCMD) Freescale Semiconductor Description Section 4.4.5, “Access Execution” for a detailed discussion of FLASH FCMD5 FCMD4 FCMD3 MC9S08AC16 Series Data Sheet, Rev ...

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... It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. 62 Description Table 4-14 Table 4-14. FLASH Commands FCMD 0x05 0x20 0x25 0x40 0x41 MC9S08AC16 Series Data Sheet, Rev. 8 Equate File Label mBlank mByteProg mBurstProg mPageErase mMassErase Freescale Semiconductor ...

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... SP is forced to 0x00FF at reset. The following sources of reset are available on the MC9S08AC16 Series: • Power-on reset (POR) • Low-voltage detect (LVD) Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Table 5-11) 63 ...

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... Bus 1 Bus = 1 ms. See t RTI Timing,” for the tolerance of this value. MC9S08AC16 Series Data Sheet, Rev. 8 Section 5.9.4, “System (SOPT2),” for additional COP Overflow Count cycles (32 ms cycles (256 ms cycles 18 2 cycles in the appendix RTI Freescale Semiconductor ...

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... The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR and PC registers to their pre-interrupt values by reading the previously saved information off the stack. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration MC9S08AC16 Series Data Sheet, Rev ...

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... INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW ² ² TOWARD HIGHER ADDRESSES ² * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08AC16 Series Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...

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... CCR the CPU will finish the current instruction, stack the PCL, PCH and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE DD – ...

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... TPM2 channel 0 TOIE TPM1 overflow CH3IE TPM1 channel 3 CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 LOLRE/LOCRE ICG LVDIE Low-voltage detect IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect — External pin — Illegal opcode Freescale Semiconductor ...

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... MCUs, the COP watchdog. To use an external clock source, it must be available and active. The RTICLKS bit in SRTISC is used to select the RTI clock source. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration level. Both the POR bit and the LVD bit in SRS are set ...

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... Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” 70 Chapter 4, “Memory,” of this data sheet for the absolute MC9S08AC16 Series Data Sheet, Rev. 8 (SRTISC),” for Freescale Semiconductor ...

Page 71

... The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...

Page 72

... Reset caused by an illegal opcode COP ILOP ILAD Writing any value to SRS address clears COP watchdog timer Note Note Figure 5-3. System Reset Status (SRS) Table 5-4. SRS Register Field Descriptions Description MC9S08AC16 Series Data Sheet, Rev ICG LVD Note 0 Freescale Semiconductor ...

Page 73

... Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to BDFR allow an external debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description 5 ...

Page 74

... Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is STOPE disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled.1Stop mode enabled STOPE 0 1 Table 5-6. SOPT Register Field Descriptions Description MC9S08AC16 Series Data Sheet, Rev Freescale Semiconductor 0 1 ...

Page 75

... Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect. Reserved 3:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[11:8] MC9S08AC16 Series is hard coded to the value 0x012. See also ID bits in Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...

Page 76

... MCU clock sources. Using external clock source the delays will be crystal frequency divided by value in RTIS2:RTIS1:RTIS0. See ID5 ID4 ID3 Description RTICLKS RTIE Description Table 5-11. MC9S08AC16 Series Data Sheet, Rev ID2 ID1 ID0 Table 5- RTIS2 RTIS1 RTIS0 Freescale Semiconductor ...

Page 77

... Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset LVDRE (provided LVDE = 1). 0 LVDF does not generate hardware resets. 1 Force an MCU reset when LVDF = 1. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Table 5-11. Real-Time Interrupt Frequency 1 1-kHz Clock Source Delay ...

Page 78

... LVD logic enabled. 0 Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage reference BGBE for use by the ADC module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. 78 Description MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 79

... Partial Power Down Acknowledge — Writing PPDACK clears the PPDF bit. PPDACK 0 Partial Power Down Control — The write-once PPDC bit controls whether stop2 or stop3 mode is selected. PPDC 0 Stop3 mode enabled. 1 Stop2, partial power down, mode enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration PPDF LVDV ...

Page 80

... Figure 5-12. System Options Register 2 (SOPT2) Table 5-14. SOPT2 Register Field Descriptions Field 7 COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog. COPCLKS 0 Internal 1-kHz clock is source to COP. 1 Bus clock is source to COP Description MC9S08AC16 Series Data Sheet, Rev Freescale Semiconductor ...

Page 81

... Freescale Semiconductor NOTE MC9S08AC16 Series Data Sheet, Rev. 8 Chapter 2, “Pins and Connections” ...

Page 82

... KBIP4–KBIP0 5 PTD1/AD1P9 PTD0/AD1P8 RxD1 TxD1 PTE7/SPSCK1 PTE6/MOSI1 RxD2 PTE5/MISO1 PTE4/SS1 TxD2 PTE3/TPM1CH1 SPSCK1 PTE2/TPM1CH0 MOSI1 PTE1/RxD1 MISO1 PTE0/TxD1 SS1 TPM1CH1 TPM1CH0 PTF6 TPM1CH3 PTF5/TPM2CH1 TPM1CH2 PTF4/TPM2CH0 PTF1/TPM1CH3 TPM2CH1 PTF0/TPM1CH2 TPM2CH0 PTG6/EXTAL TPM3CH1 PTG5/XTAL TPM3CH0 PTG4/KBIP4 PTG3/KBIP3 PTG2/KBIP2 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 83

... The pin control registers, pullup enable (PTAPE), slew rate control (PTASE), and drive strength select (PTADS) are located in the high page registers. Refer to Section 6.4, “Parallel I/O general-purpose I/O control and Freescale Semiconductor Chapter 2, “Pins and ...

Page 84

... C pins Configuration” for more information about using MC9S08AC16 Series Data Sheet, Rev PTB3/ PTB2/ PTB1/ TPM3CH1/ AD1P1 AD1P3 AD1P2 (S08ADC10V1)” for more PTC3/ PTC2/ PTC1/ PTC0/ TxD2 MCLK SDA1 SCL1 Freescale Semiconductor Bit 0 PTB0/ AD1P0 Bit 0 ...

Page 85

... I/O port. Also, for pins which are configured as outputs by the shared function, the output data is controlled by the shared function and not by the port data register. Freescale Semiconductor 6 5 ...

Page 86

... Control” for more information about Section 6.5, “Pin Control” for more information about pin control. MC9S08AC16 Series Data Sheet, Rev. 8 for more information about using PTF1 TPM1CH3 TPM1CH2 Bit 0 PTG3/ PTG2/ PTG1/ PTG0/ KBIP3 KBIP2 KBIP1 KBIP0 Freescale Semiconductor Bit 0 PTF0/ ...

Page 87

... In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function Freescale Semiconductor (S08ICGV4)” for more information about using port G pins (S08KBIV1)” for more information about using port G pins as ...

Page 88

... DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this the EMC emissions may be affected by enabling pins as high drive. 88 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 89

... Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor ...

Page 90

... Internal pullup device disabled for port A bit n. 1 Internal pullup device enabled for port A bit Table 6-2. PTADD Register Field Descriptions Description Table 6-3. PTAPE Register Field Descriptions Description MC9S08AC16 Series Data Sheet, Rev PTADD2 PTADD1 PTAPE2 PTAPE1 Freescale Semiconductor 0 PTADD0 0 0 PTAPE0 0 ...

Page 91

... Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high PTADSn output drive for the associated PTA pin. 0 Low output drive enabled for port A bit n. 1 High output drive enabled for port A bit n. Freescale Semiconductor ...

Page 92

... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBD3 0 0 Figure 6-15. Port B Data Register (PTBD) Table 6-6. PTBD Register Field Descriptions Description PTBDD3 0 0 Description MC9S08AC16 Series Data Sheet, Rev PTBD2 PTBD1 PTBDD2 PTBDD1 Freescale Semiconductor 0 PTBD0 0 0 PTBDD0 0 ...

Page 93

... Output Slew Rate Control Enable for Port B Bits— Each of these control bits determine whether output slew PTBSE[3:0] rate control is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. Freescale Semiconductor PTBPE3 ...

Page 94

... Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled PTBDS3 Description PTCD5 PTCD4 PTCD3 Figure 6-20. Port C Data Register (PTCD) Description MC9S08AC16 Series Data Sheet, Rev PTBDS2 PTBDS1 PTBDS0 PTCD2 PTCD1 PTCD0 Freescale Semiconductor ...

Page 95

... PTC pin. For port C pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pullup device disabled for port C bit n. 1 Internal pullup device enabled for port C bit n. Freescale Semiconductor ...

Page 96

... PTC pin. 0 Low output drive enabled for port C bit n. 1 High output drive enabled for port C bit PTCSE5 PTCSE4 PTCSE3 Description PTCDS5 PTCDS4 PTCDS3 Description MC9S08AC16 Series Data Sheet, Rev PTCSE2 PTCSE1 PTCSE0 PTCDS2 PTCDS1 PTCDS0 Freescale Semiconductor ...

Page 97

... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[3:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. Freescale Semiconductor ...

Page 98

... PTD pin. For port D pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit PTDPE3 Description PTDSE3 Description MC9S08AC16 Series Data Sheet, Rev PTDPE2 PTDPE1 PTDPE0 PTDSE2 PTDSE1 PTDSE0 Freescale Semiconductor ...

Page 99

... Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor ...

Page 100

... Internal pullup device disabled for port E bit n. 1 Internal pullup device enabled for port E bit n. 100 PTEDD5 PTEDD4 PTEDD3 Description PTEPE5 PTEPE4 PTEPE3 Description MC9S08AC16 Series Data Sheet, Rev PTEDD2 PTEDD1 PTEDD0 PTEPE2 PTEPE1 PTEPE0 Freescale Semiconductor ...

Page 101

... Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. 0 Low output drive enabled for port E bit n. 1 High output drive enabled for port E bit n. Freescale Semiconductor PTESE5 ...

Page 102

... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn. 102 PTFD5 PTFD4 Figure 6-35. Port F Data Register (PTFD) Description PTFDD5 PTFDD4 Description MC9S08AC16 Series Data Sheet, Rev PTFD1 PTFD0 PTFDD1 PTFDD0 Freescale Semiconductor ...

Page 103

... PTFSEn rate control is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port F bit n. 1 Output slew rate control enabled for port F bit n. Freescale Semiconductor PTFPE5 PTFPE4 ...

Page 104

... PTFDS5 PTFDS4 0 0 Description 5 4 PTGD5 PTGD4 PTGD3 0 0 Figure 6-40. Port G Data Register (PTGD) Table 6-31. PTGD Register Field Descriptions Description MC9S08AC16 Series Data Sheet, Rev PTFDS1 PTGD2 PTGD1 Freescale Semiconductor 0 PTFDS0 0 0 PTGD0 0 ...

Page 105

... PTG pin. For port G pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pullup device disabled for port G bit n. 1 Internal pullup device enabled for port G bit n. Freescale Semiconductor ...

Page 106

... PTG pin. 0 Low output drive enabled for port G bit n. 1 High output drive enabled for port G bit n. 106 PTGSE5 PTGSE4 PTGSE3 Description PTGDS5 PTGDS4 PTGDS3 Description MC9S08AC16 Series Data Sheet, Rev PTGSE2 PTGSE1 PTGSE0 PTGDS2 PTGDS1 PTGDS0 Freescale Semiconductor ...

Page 107

... Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 107 ...

Page 108

... X. 108 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 109

... Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1. CONDITION CODE REGISTER Freescale Semiconductor ...

Page 110

... Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location 110 Table 7-1. CCR Register Field Descriptions Description MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 111

... Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Chapter 7 Central Processor Unit (S08CPUV2) ...

Page 112

... The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional information about these operations. 112 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 113

... The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program not asynchronous to program execution. Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08AC16 Series Data Sheet, Rev. 8 ...

Page 114

... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. 114 chapter for more details. MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 115

... Arithmetic Shift Left ASLA ASLX C ASL oprx8,X b7 ASL ,X ASL oprx8,SP (Same as LSL) ASR opr8a Arithmetic Shift Right ASRA ASRX ASR oprx8,X ASR , ASR oprx8,SP Freescale Semiconductor Object Code IMM DIR EXT IX2 IX1 IX SP2 9E D9 SP1 9E E9 IMM DIR EXT IX2 IX1 IX ...

Page 116

... Freescale Semiconductor – ...

Page 117

... Clear Interrupt Mask Bit (I ← 0) CLI M ← $00 CLR opr8a Clear A ← $00 CLRA X ← $00 CLRX H ← $00 CLRH M ← $00 CLR oprx8,X M ← $00 CLR ,X M ← $00 CLR oprx8,SP Freescale Semiconductor Object Code REL 2A rr REL 20 rr DIR (b0) 01 DIR (b1) 03 DIR (b2) 05 DIR (b3) 07 DIR (b4) 09 DIR (b5) ...

Page 118

... Freescale Semiconductor – 1 – – – – – ...

Page 119

... Logical Shift Left LSLA LSLX C LSL oprx8,X b7 LSL ,X (Same as ASL) LSL oprx8,SP LSR opr8a Logical Shift Right LSRA LSRX 0 LSR oprx8,X LSR ,X b7 LSR oprx8,SP Freescale Semiconductor Object Code DIR INH INH IX1 IX SP1 9E 6C DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 ...

Page 120

... Freescale Semiconductor Affect – – – – – ...

Page 121

... Enable Interrupts: Stop Processing STOP Refer to MCU Documentation I bit ← 0; Stop Processing STX opr8a STX opr16a STX oprx16,X Store X (Low 8 Bits of Index Register) STX oprx8,X in Memory M ← (X) STX ,X STX oprx16,SP STX oprx8,SP Freescale Semiconductor Object Code INH 9C INH 80 INH 81 IMM A2 DIR B2 EXT C2 ...

Page 122

... Freescale Semiconductor – ...

Page 123

... Loaded with : Concatenated with CCR Bits: V Overflow bit H Half-carry bit I Interrupt mask N Negative bit Z Zero bit C Carry/borrow bit Freescale Semiconductor Object Code INH 94 INH 8F Addressing Modes: DIR Direct addressing mode EXT Extended addressing mode IMM Immediate addressing mode INH Inherent addressing mode IX ...

Page 124

... IMM 2 DIR 3 EXT 3 IX2 TXA AIX STX STX STX INH 2 IMM 2 DIR 3 EXT 3 IX2 Opcode HCS08 Cycles Hexadecimal SUB Instruction Mnemonic Addressing Mode Number of Bytes 1 IX Freescale Semiconductor SUB SUB 2 IX1 CMP CMP 2 IX1 SBC SBC 2 IX1 CPX CPX 2 IX1 1 IX ...

Page 125

... EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control 9E60 6 NEG 3 SP1 9E61 6 CBEQ 4 SP1 ...

Page 126

... Chapter 7 Central Processor Unit (S08CPUV2) 126 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 127

... ICGLCLK is the alternate BDC clock source for the MC9S08AC16 Series. * XCLK is the fixed-frequency clock. Figure 8-1. System Clock Distribution Diagram Freescale Semiconductor recommends that FLASH location 0xFFBE be reserved to store a nonvolatile version of ICGTRM. This will allow debugger and programmer vendors to perform a manual trim operation and store the resultant ICGTRM value for users to access at a later time ...

Page 128

... KBIP4–KBIP0 5 PTD1/AD1P9 PTD0/AD1P8 RxD1 TxD1 PTE7/SPSCK1 PTE6/MOSI1 RxD2 PTE5/MISO1 PTE4/SS1 TxD2 PTE3/TPM1CH1 SPSCK1 PTE2/TPM1CH0 MOSI1 PTE1/RxD1 MISO1 PTE0/TxD1 SS1 TPM1CH1 TPM1CH0 PTF6 TPM1CH3 PTF5/TPM2CH1 TPM1CH2 PTF4/TPM2CH0 PTF1/TPM1CH3 TPM2CH1 PTF0/TPM1CH2 TPM2CH0 PTG6/EXTAL TPM3CH1 PTG5/XTAL TPM3CH0 PTG4/KBIP4 PTG3/KBIP3 PTG2/KBIP2 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 129

... Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates MHz) — Uses external or internal clock as reference frequency • Automatic lockout of non-running clock sources • Reset or interrupt on loss of clock or loss of FLL lock Freescale Semiconductor Section 8.5, “Initialization/Application MC9S08AC16 Series Data Sheet, Rev. 8 Internal Clock Generator (S08ICGV4) Figure 8-3, the ICG consists ...

Page 130

... The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the external reference. 130 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 131

... If upon the first write to ICGC1, either the FEI mode or SCM mode is selected, this pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. Freescale Semiconductor ICG SELECT ...

Page 132

... ICG EXTAL V SS CLOCK INPUT Figure 8-4. External Clock Connections ICG EXTAL CRYSTAL OR RESONATOR Memory chapter of this data sheet for the absolute address MC9S08AC16 Series Data Sheet, Rev. 8 Figure 8-4. XTAL NOT CONNECTED Electrical Characteristics chapter. XTAL R S Freescale Semiconductor ...

Page 133

... Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. Freescale Semiconductor 5 4 REFS CLKS 0 0 Figure 8-6 ...

Page 134

... Division factor = 1 001 Division factor = 2 010 Division factor = 4 011 Division factor = 8 100 Division factor = 16 101 Division factor = 32 110 Division factor = 64 111 Division factor = 128 134 MFD LOCRE Figure 8-7. ICG Control Register 2 (ICGC2) Description MC9S08AC16 Series Data Sheet, Rev RFD Freescale Semiconductor ...

Page 135

... ICGIF would remain set after the clear sequence was completed for the earlier interrupt. Writing a logic 0 to ICGIF has no effect ICG interrupt request is pending ICG interrupt request is pending. Freescale Semiconductor REFST ...

Page 136

... ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. 136 Figure 8-9. ICG Status Register 2 (ICGS2) Description for two consecutive samples and the DCO clock is not static. This bit is unlock Description MC9S08AC16 Series Data Sheet, Rev DCOS FLT Freescale Semiconductor ...

Page 137

... The ICG is very flexible, and in some configurations possible to exceed certain clock specifications. When using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation. Freescale Semiconductor ...

Page 138

... ICGOUT will double if the FLL was unlocked. ICGDCLK If this mode is entered from off mode, f 138 will default to f ICGDCLK Self_reset will maintain the previous frequency.If this mode ICGDCLK will be equal to the frequency of ICGDCLK before ICGDCLK MC9S08AC16 Series Data Sheet, Rev. 8 which is nominally 8 MHz. If this Freescale Semiconductor ...

Page 139

... The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01 In FLL engaged internal mode, the reference clock is derived from the internal reference clock ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. Freescale Semiconductor CLKS ICGIRCLK CLOCK ...

Page 140

... DCO, the reference clock cannot be any faster than 10 MHz. 140 or less than the minimum n unlock (max) and greater than n (min) for a given number of samples, as lock Table 8- Because MHz is 40MHz, which is the MC9S08AC16 Series Data Sheet, Rev required by the unlock or less than lock / R. ICGDCLK / external clock ICGERCLK Freescale Semiconductor ...

Page 141

... Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the LOLS will not be set. Freescale Semiconductor , as required by the lock detector to detect the unlock / R ...

Page 142

... Forced High 1 Real-Time X Real-Time X Forced Low X Real-Time 0 Forced High 1 Real-Time X Real-Time MC9S08AC16 Series Data Sheet, Rev. 8 Table 8-8). Provided DCO Clock Clock Monitored? Monitored (1) Yes Yes (2) No Yes (2) Yes Yes (2) Yes Yes No Yes Yes Yes No No Yes No Yes Yes Freescale Semiconductor ...

Page 143

... The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons that determine the DCOS bit 3 After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are changed. Freescale Semiconductor Table 8-9 NOTE Table 8-9. ICG State Table ...

Page 144

... For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. 144 Table Table 8-12). MC9S08AC16 Series Data Sheet, Rev. 8 8-11), N and R are determined by Freescale Semiconductor ...

Page 145

... MFD Value Multiplication Factor (N) 000 4 001 6 010 8 011 10 100 12 Freescale Semiconductor FEE 4 MHz < f Medium power (will be less than FEI if oscillator range = low) High clock accuracy Medium/High system cost (crystal, resonator or external clock source required) 1 IRG is off. DCO is on. FBE f Bus used ...

Page 146

... FLL engaged, external reference clock mode Oscillator disabled Loss-of-clock detection enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08AC16 Series Data Sheet, Rev. 8 ÷32 ÷64 ÷128 ). Bus = 32 kHz Freescale Semiconductor Eqn. 8-1 Eqn. 8-2 ...

Page 147

... RESET INITIALIZE ICG ICGC1 = $38 ICGC2 = $00 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Figure 8-14. ICG Initialization for FEE in Example #1 Freescale Semiconductor QUICK RECOVERY FROM STOP MINIMUM CURRENT DRAW IN STOP RECOVERY FROM STOP OSCSTEN = 1 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE ...

Page 148

... Requests an oscillator FLL engaged, external reference clock mode Disables the oscillator Loss-of-clock detection enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08AC16 Series Data Sheet, Rev Bus Eqn. 8-3 Eqn. 8-4 Freescale Semiconductor ...

Page 149

... FLL LOCK STATUS Figure 8-15. ICG Initialization and Stop Recovery for Example #2 Freescale Semiconductor RECOVERY RESET FROM STOP INITIALIZE ICG SERVICE INTERRUPT ICGC1 = $7A ICGC2 = $30 SOURCE (f CHECK NO LOCK = 1? FLL LOCK STATUS LOCK = 1? YES CONTINUE CONTINUE MC9S08AC16 Series Data Sheet, Rev. 8 Internal Clock Generator (S08ICGV4) ...

Page 150

... Oscillator using crystal or resonator requested (bit is really a don’t care) FLL engaged, internal reference clock mode Disables the oscillator Loss-of-clock enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08AC16 Series Data Sheet, Rev Bus = 243 kHz Freescale Semiconductor Eqn. 8-5 Eqn. 8-6 ...

Page 151

... CHECK FLL LOCK STATUS. LOCK = 1? CONTINUE Figure 8-16. ICG Initialization and Stop Recovery for Example #3 Freescale Semiconductor Only need to write when trimming internal oscillator; done in separate operation (see example #4) NO YES NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE ...

Page 152

... COUNT = EXPECTED = 500 . CASE STATEMENT COUNT > EXPECTED = 500 (RUNNING TOO FAST) ICGTRM = ICGTRM + 128 / (2**n) (INCREASING ICGTRM DECREASES THE FREQUENCY YES IS n > Figure 8-17. Trim Procedure MC9S08AC16 Series Data Sheet, Rev. 8 STORE ICGTRM VALUE IN NON-VOLATILE MEMORY CONTINUE Figure 8-17 while the Freescale Semiconductor ...

Page 153

... Choice of edge-only or edge-and-level sensitivity • Common interrupt flag and interrupt enable control • Capable of waking up the MCU from stop3, stop2, or wait mode Freescale Semiconductor Connections,” for more information about the logic and NOTE (KBIPE).” MC9S08AC16 Series Data Sheet, Rev. 8 (KBISC),” ...

Page 154

... KBIP4–KBIP0 5 PTD1/AD1P9 PTD0/AD1P8 RxD1 TxD1 PTE7/SPSCK1 PTE6/MOSI1 RxD2 PTE5/MISO1 PTE4/SS1 TxD2 PTE3/TPM1CH1 SPSCK1 PTE2/TPM1CH0 MOSI1 PTE1/RxD1 MISO1 PTE0/TxD1 SS1 TPM1CH1 TPM1CH0 PTF6 TPM1CH3 PTF5/TPM2CH1 TPM1CH2 PTF4/TPM2CH0 PTF1/TPM1CH3 TPM2CH1 PTF0/TPM1CH2 TPM2CH0 PTG6/EXTAL TPM3CH1 PTG5/XTAL TPM3CH0 PTG4/KBIP4 PTG3/KBIP3 PTG2/KBIP2 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 155

... Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor V DD CLR ...

Page 156

... Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = 0) 0 Edge-only detection 1 Edge-and-level detection 156 KBF KBEDG5 KBEDG4 Description MC9S08AC16 Series Data Sheet, Rev KBIE KBIMOD KBACK Freescale Semiconductor ...

Page 157

... When the MCU enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop mode. Freescale Semiconductor 5 4 KBIPE5 ...

Page 158

... When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard input is at its asserted level. 158 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 159

... Timer system enable • One interrupt per channel plus a terminal count interrupt for each TPM module Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Section 8.4.11, “Fixed 159 ...

Page 160

... KBIP4–KBIP0 5 PTD1/AD1P9 PTD0/AD1P8 RxD1 TxD1 PTE7/SPSCK1 PTE6/MOSI1 RxD2 PTE5/MISO1 PTE4/SS1 TxD2 PTE3/TPM1CH1 SPSCK1 PTE2/TPM1CH0 MOSI1 PTE1/RxD1 MISO1 PTE0/TxD1 SS1 TPM1CH1 TPM1CH0 PTF6 TPM1CH3 PTF5/TPM2CH1 TPM1CH2 PTF4/TPM2CH0 PTF1/TPM1CH3 TPM2CH1 PTF0/TPM1CH2 TPM2CH0 PTG6/EXTAL TPM3CH1 PTG5/XTAL TPM3CH0 PTG4/KBIP4 PTG3/KBIP3 PTG2/KBIP2 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 161

... In BDM mode, a write to TPMxCnSC Write to TPMxCnVH:L registers In Input Capture mode, writes to TPMxCnVH:L registers In Output Compare mode, when (CLKSB:CLKSA not = 0:0), 3 writes to TPMxCnVH:L registers Freescale Semiconductor TPMV3 Clears the TPM counter (TPMxCNTH:L) and the prescaler counter. Returns the value of the TPM counter that is frozen. ...

Page 162

... Produces 0% duty cycle. Produces 0% duty cycle. Changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). Finishes the current PWM period using the new duty cycle setting. Does not clear the write coherency mechanism. (TPMxCnVH:TPMxCnVL).” Freescale Semiconductor ...

Page 163

... Updating the Channel Value Register (TPMxCnV) register in edge-aligned or center-aligned modes... Reseting the coherency mechanism for the Channel Value Register (TPMxCnV) register... Configuring the TPM modules... Freescale Semiconductor Mode.” [SE110-TPM case 4] Versions,” keep in mind the following Action / Best Practice Timer must be in Input Capture mode. ...

Page 164

... MCU pin. The output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). 164 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 165

... Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Timer/PWM Module (S08TPMV3) ...

Page 166

... MC9S08AC16 Series Data Sheet, Rev. 8 PRESCALE AND SELECT ³ 16, 32, 64, or ³128 PS2:PS1:PS0 INTER- TOF RUPT TOIE LOGIC PORT TPMxCH0 LOGIC INTER- RUPT LOGIC CH0IE PORT TPMxCH1 LOGIC INTER- RUPT LOGIC CH1IE PORT TPMxCH7 LOGIC INTER- RUPT LOGIC CH7IE Freescale Semiconductor ...

Page 167

... TPM, refer to full-chip documentation for a specific derivative for more details about the interaction of TPM pin functions and general purpose I/O controls including port data, data direction, and pullup controls. Freescale Semiconductor Table 10-3. Signal Properties Function MC9S08AC16 Series Data Sheet, Rev. 8 ...

Page 168

... When the output compare toggle mode is initially selected, the previous value on the pin is driven out until the next output compare event—then the pin is toggled. 168 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 169

... TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT Figure 10-3. High-True Pulse of an Edge-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT Figure 10-4. Low-True Pulse of an Edge-Aligned PWM Freescale Semiconductor ... ... ...

Page 170

... TPMxCHn CHnF BIT TOF BIT Figure 10-5. High-True Pulse of a Center-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 TPMxCHn CHnF BIT TOF BIT Figure 10-6. Low-True Pulse of a Center-Aligned PWM 170 MC9S08AC16 Series Data Sheet, Rev Freescale Semiconductor 5 ... 5 ... ...

Page 171

... CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS. 0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register. 1 All channels operate in center-aligned PWM mode. Freescale Semiconductor ...

Page 172

... TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disable) 01 Bus rate clock 10 Fixed system clock 11 External source Table 10-6. Prescale Factor Selection TPM Clock Source Divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 173

... If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is active or not). Freescale Semiconductor ...

Page 174

... TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function CHnF CHnIE W 0 Reset Unimplemented or Reserved Figure 10-12. TPM Channel n Status and Control Register (TPMxCnSC) 174 MSnB MSnA ELSnB MC9S08AC16 Series Data Sheet, Rev Bit Bit ELSnA Freescale Semiconductor ...

Page 175

... I/O pin when the associated timer channel is set software timer that does not require the use of a pin. Table 10-8. Mode, Edge, and Level Selection CPWMS MSnB:MSnA X XX Freescale Semiconductor Table 10-7. TPMxCnSC Field Descriptions Description Table 10-8 ELSnB:ELSnA Mode 00 ...

Page 176

... Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up Bit Bit Freescale Semiconductor ...

Page 177

... TPM status and control register because it affects all channels within the TPM and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.) Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Timer/PWM Module (S08TPMV3) ...

Page 178

... TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility 178 Table 10-9. TPM Clock Source Selection TPM Clock Source to Prescaler Input No clock selected (TPM counter disabled) Bus rate clock Fixed system clock External source MC9S08AC16 Series Data Sheet, Rev. 8 Table 10-5. After any MCU reset, Freescale Semiconductor ...

Page 179

... Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and edge-aligned PWM. Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Timer/PWM Module (S08TPMV3) ...

Page 180

... If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare forces the PWM signal high. 180 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 181

... TPMxMODH:TPMxMODL=0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. Freescale Semiconductor OVERFLOW PERIOD OUTPUT ...

Page 182

... Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 182 COUNT= 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT DOWN) (COUNT UP) PULSE WIDTH 2 x TPMxCnVH:TPMxCnVL PERIOD 2 x TPMxMODH:TPMxMODL MC9S08AC16 Series Data Sheet, Rev. 8 COUNT= TPMxMODH:TPMxMODL Freescale Semiconductor ...

Page 183

... For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by software to determine that the action has occurred associated enable bit (TOIE or CHnIE) can be set Freescale Semiconductor Table 10-10 which shows the interrupt name, the name of any local enable Table 10-10 ...

Page 184

... When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step sequence described Section 10.8.2, “Description of Interrupt Operation.” 184 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 185

... Output Compare Mode In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer at the next change of the TPM counter (end of the Freescale Semiconductor (Section 10.5.2, “TPM-Counter Registers (Section 10.5.2, “TPM-Counter Registers (Section 10.5.5, “TPM Channel Value Registers (Section 10.6.2.1, “ ...

Page 186

... In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). 186 (Section 10.6.2.3, “Edge-Aligned PWM (Section 10.6.2.4, “Center-Aligned PWM MC9S08AC16 Series Data Sheet, Rev. 8 Mode) Mode) Mode) Freescale Semiconductor ...

Page 187

... TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure 10-17. Generation of high-true EPWM signal by TPM v2 and v3 after the reset Freescale Semiconductor (Section 10.5.3, “TPM Counter Modulo show when the EPWM signals generated by TPM v2 and TPM 0 00 MC9S08AC16 Series Data Sheet, Rev. 8 ...

Page 188

... TPM does not control the channel pin, so the EPWM signal is not available); wait until the TOF is set (or use the TOF interrupt); enable the channel output by configuring ELSnB:ELSnA bits (now EPWM signal is available); ... 188 0 00 MC9S08AC16 Series Data Sheet, Rev Freescale Semiconductor 2 ... ...

Page 189

... Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. Ignore any references to stop1 low-power mode in this chapter, because the MC9S08AC16 Series does not support it. Freescale Semiconductor NOTE MC9S08AC16 Series Data Sheet, Rev. 8 189 ...

Page 190

... KBIP4–KBIP0 5 PTD1/AD1P9 PTD0/AD1P8 RxD1 TxD1 PTE7/SPSCK1 PTE6/MOSI1 RxD2 PTE5/MISO1 PTE4/SS1 TxD2 PTE3/TPM1CH1 PTE2/TPM1CH0 SPSCK1 MOSI1 PTE1/RxD1 MISO1 PTE0/TxD1 SS1 TPM1CH1 TPM1CH0 PTF6 TPM1CH3 PTF5/TPM2CH1 TPM1CH2 PTF4/TPM2CH0 PTF1/TPM1CH3 TPM2CH1 PTF0/TPM1CH2 TPM2CH0 PTG6/EXTAL TPM3CH1 PTG5/XTAL TPM3CH0 PTG4/KBIP4 PTG3/KBIP3 PTG2/KBIP2 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 191

... Modes of Operation See Section 11.3, “Functional Description,” For details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode Freescale Semiconductor MC9S08AC16 Series Data Sheet, Rev. 8 Serial Communications Interface (S08SCIV4) 191 ...

Page 192

... SHIFT DIRECTION T8 PARITY GENERATION TRANSMIT CONTROL TDRE TIE TC TCIE Figure 11-2. SCI Transmitter Block Diagram MC9S08AC16 Series Data Sheet, Rev. 8 LOOPS RSRC LOOP TO RECEIVE CONTROL DATA IN TO TxD PIN TXINV SCI CONTROLS TxD TO TxD PIN LOGIC TxD DIRECTION Tx INTERRUPT REQUEST Freescale Semiconductor ...

Page 193

... INTERNAL BUS 16 × BAUD RATE CLOCK FROM TRANSMITTER LOOPS SINGLE-WIRE LOOP CONTROL RSRC FROM RxD PIN RXINV DATA RECOVERY ACTIVE EDGE DETECT PE PT Freescale Semiconductor (READ-ONLY) DIVIDE SCID – Rx BUFFER BY 16 11-BIT RECEIVE SHIFT REGISTER M LBKDE WAKE WAKEUP LOGIC ILT RDRF ...

Page 194

... Figure 11-5. SCI Baud Rate Register (SCIxBDL) 194 Memory chapter of this data sheet for the absolute address SBR12 SBR11 Table 11-1. SCIxBDH Field Descriptions Description SBR5 SBR4 SBR3 MC9S08AC16 Series Data Sheet, Rev SBR10 SBR9 SBR8 SBR2 SBR1 SBR0 Freescale Semiconductor ...

Page 195

... Refer to Section 11.3.3.2.1, “Idle-Line 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. Freescale Semiconductor Table 11-2. SCIxBDL Field Descriptions Description 5 ...

Page 196

... When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. 196 Description RIE ILIE Table 11-4. SCIxC2 Field Descriptions Description Idle” for more details. MC9S08AC16 Series Data Sheet, Rev RWU SBK Freescale Semiconductor ...

Page 197

... This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status flags TDRE TC W Reset Unimplemented or Reserved Freescale Semiconductor Description Section 11.3.3.2, “Receiver Wakeup 5 4 RDRF IDLE Figure 11-8. SCI Status Register 1 (SCIxS1) MC9S08AC16 Series Data Sheet, Rev. 8 Serial Communications Interface (S08SCIV4) Operation” ...

Page 198

... NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD noise detected. 1 Noise detected in the received character in SCIxD. 198 Table 11-5. SCIxS1 Field Descriptions Description MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 199

... Break Character Generation Length — BRK13 is used to select a longer transmitted break character length. BRK13 Detection of a framing error is not affected by the state of this bit. 0 Break character is transmitted with length of 10 bit times ( Break character is transmitted with length of 13 bit times ( Freescale Semiconductor Description ...

Page 200

... RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. 200 Description TXDIR TXINV ORIE Table 11-7. SCIxC3 Field Descriptions Description MC9S08AC16 Series Data Sheet, Rev NEIE FEIE PEIE Freescale Semiconductor ...

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