MC9S08AC16CFJE Freescale Semiconductor, MC9S08AC16CFJE Datasheet - Page 314

• Manufacturer Part Number: MC9S08AC16CFJE
• Description: IC MCU 8BIT 16K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC16CFJE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Appendix A Electrical Characteristics and Timing Specifications
A.11 SPI Characteristics
Table A-14
314
1
2
3
and
Num
All timing is shown with respect to 20% V
Time to data active from high-impedance state.
Hold time to high-impedance state.
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
10
11
1
2
3
4
5
6
7
8
9
Figure A-15
C
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time
Master and Slave
Clock (SPSCK) low time Master
and Slave
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
through
Characteristic
Table A-14. SPI Electrical Characteristic
MC9S08AC16 Series Data Sheet, Rev. 8
Figure A-18
2
3
1
Master
Master
Master
Master
Master
Master
Master
Master
DD
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
and 70% V
describe the timing requirements for the SPI system.
Symbol
t
t
t
t
t
t
t
t
SCKH
SCKL
t
t
SI(M)
HI(M)
t
t
SI(S)
HI(S)
Lead
Lead
t
t
t
t
SCK
SCK
t
f
f
Lag
Lag
SO
SO
HO
HO
t
dis
op
op
A
DD
, unless noted; 100 pF load on all SPI
1/2 t
1/2 t
f
Bus
SCK
SCK
Min
–10
–10
1/2
1/2
dc
30
30
30
30
25
25
—
—
—
/2048
2
4
0
– 25
– 25
f
f
2048
Bus
Bus
Max
1/2
1/2
—
—
—
—
—
—
—
—
—
40
40
—
—
—
—
/2
/4
Freescale Semiconductor
t
t
t
t
Unit
SCK
SCK
SCK
SCK
t
t
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc