MC9S08AC16CFJE Freescale Semiconductor, MC9S08AC16CFJE Datasheet - Page 77

• Manufacturer Part Number: MC9S08AC16CFJE
• Description: IC MCU 8BIT 16K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC16CFJE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.9.8
Freescale Semiconductor
LVDACK
Reset
LVDRE
LVDIE
Field
LVDF
1
7
6
5
4
W
R
Normal values are shown in this column based on f
Timing
RTIS2:RTIS1:RTIS0
1
2
Bit 1 is a reserved bit that must always be written to 0.
This bit can be written only one time after reset. Additional writes are ignored.
System Power Management Status and Control 1 Register (SPMSC1)
LVDF
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
Specifications,” f
0
7
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
= Unimplemented or Reserved
LVDACK
0
0
6
RTI
Table 5-12. SPMSC1 Register Field Descriptions
for the tolerance on these values.
Table 5-11. Real-Time Interrupt Frequency
Disable periodic wakeup timer
1-kHz Clock Source Delay
MC9S08AC16 Series Data Sheet, Rev. 8
LVDIE
0
5
128 ms
256 ms
512 ms
1.024 s
32 ms
64 ms
8 ms
LVDRE
RTI
1
4
= 1 kHz. See
2
Description
1
LVDSE
Chapter 5 Resets, Interrupts, and System Configuration
3
1
Appendix A, “Electrical Characteristics and
2
Using External Clock Source Delay
Disable periodic wakeup timer
LVDE
(Crystal Frequency)
1
2
divide by 16384
divide by 32768
divide by 2048
divide by 4096
divide by 8192
divide by 1024
divide by 256
2
1
0
1
BGBE
0
0
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