Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 36

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 8. Reset and Stop Mode Recovery Characteristics and Latency (Continued)
PS026308-1207
Reset Type
Stop Mode Recovery
Stop Mode Recovery with
crystal oscillator enabled
During a system Reset or Stop Mode Recovery, the Z8 Encore! F083A Series device is
held in reset for about 66 cycles of the internal precision oscillator. If the crystal oscillator
is enabled in the Flash option bits, the reset period is increased to about 5000 IPO cycles.
When a reset occurs because of a low voltage condition or POR, the reset delay is
measured from the time the supply voltage first exceeds the POR level (discussed later in
this chapter). If the external pin reset remains asserted at the end of the reset period, the
device remains in reset until the pin is deasserted.
At the beginning of reset, all GPIO pins are configured as inputs with pull-up resistor
disabled, except PD0 which is shared with the reset pin. On Reset, the Port D0 pin is
configured as a bidirectional open-drain reset. This pin is internally driven low during port
reset, after which the user code reconfigures this pin as a general purpose output.
During reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer Oscillator continues to run.
On reset, control registers within the Register File that have a defined reset value are
loaded with their reset values. Other control registers (including the Stack Pointer,
Register Pointer, and Flags) and general purpose RAM are undefined following the reset.
The eZ8 CPU fetches the reset vector at program memory addresses
and loads that value into the program counter. Program execution begins at the reset vector
address.
Because the control registers are re-initialized by a system reset, the system clock after
reset is always the IPO. User software must reconfigure the oscillator control block, to
enable and select the correct system clock source.
Control Registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
Reset Characteristics and Latency
Reset About 66 internal precision oscillator cycles
Reset About 5000 internal precision oscillator
CPU
eZ8
Reset Latency (Delay)
cycles
Z8 Encore!
Reset and Stop Mode Recovery
Product Specification
0002H
®
F083A Series
and
0003H
24