Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 76

IC ENCORE XP MCU FLASH 8K 28SOIC

Z8F083ASJ020EG

Manufacturer Part Number
Z8F083ASJ020EG
Description
IC ENCORE XP MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!®r
Datasheet

Specifications of Z8F083ASJ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Other names
269-4558-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F083ASJ020EG
Manufacturer:
Zilog
Quantity:
363
Table 45. Shared Interrupt Select Register (IRQSS)
Table 46. Interrupt Control Register (IRQCTL)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Interrupt Control Register
Reserved
IRQE
R/W
R/W
7
0
7
0
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
PA6CS—PA6/Comparator selection
0 = PA6 is used for the interrupt caused by PA6CS interrupt request.
1 = The comparator is used for the interrupt caused by PA6CS interrupt request.
Reserved—Must be 0.
The interrupt control (IRQCTL) register contains the master enable bit for all interrupts.
See
IRQE—Interrupt request enable
This bit is set to 1 by executing an EI (enable interrupts) or IRET (interrupt return)
instruction, or by a direct register write of 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, reset or by a direct register
write of a 0 to this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0.
Table
PA6CS
R/W
46.
R
6
0
6
0
R/W
R
5
0
5
0
R/W
R
4
0
4
0
FCEH
FCFH
Reserved
R/W
R
3
0
3
0
Reserved
R/W
Z8 Encore!
R
2
0
2
0
Product Specification
R/W
R
1
0
1
0
®
Interrupt Controller
F083A Series
R/W
R
0
0
0
0
64

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