Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 96

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

PS026308-1207
Caution:
Caution:
PRES—Prescale value.
The timer input clock is divided by 2
reset each time the timer is disabled. This reset ensures proper clock division each time the
timer is restarted.
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When the timer output alternate function TxOUT on a GPIO port pin is enabled, TxOUT
will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the port data direction sub register is not needed to be set to
output on TxOUT. Changing the TPOL bit when the timer is enabled and running does
not immediately change the polarity TxOUT.
PWM DUAL OUTPUT Mode
0 = Timer output is forced low (0) and timer output complement is forced high (1),
when the timer is disabled. When enabled and the PWM count matches, the timer
output is forced high (1) and forced low (0) when enabled and reloaded. When
enabled and the PWM count matches, the timer output complement is forced low (0)
and forced high (1) when enabled and reloaded.
1 = Timer output is forced high (1) and timer output complement is forced low (0)
when the timer is disabled. When enabled and the PWM count matches, the timer
output is forced low (0) and forced high (1) when enabled and reloaded.When enabled
and the PWM count matches, the timer output complement is forced high (1) and
forced low (0) when enabled and reloaded. The PWMD field in the TxCTL0 register
determiners an optional added delay on the assertion (low to high) transition of both
timer output and timer output complement for deadband generation.
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARATOR COUNTER Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled, the timer output signal is complemented on timer reload.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
PRES
, where PRES is set from 0 to 7. The prescaler is
Z8 Encore!
Product Specification
®
F083A Series
Timers
84