Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 59

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 21. Port A–D High Drive Enable Subregisters (PxHDE)
Table 22. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
PSMRE7
PHDE7
R/W
R/W
If 04H in Port A–D Address Register, accessible through the Port A–D Control Register
If 05H in Port A–D Address Register, accessible through the Port A–D Control Register
7
0
7
0
0 = The drains are enabled for any output mode (unless overridden by the alternate function).
1 = The drain of the associated pin is disabled (OPEN-DRAIN mode).
Port A–D High Drive Enable Subregisters
The Port A–D high drive enable subregister is accessed through the Port
A–D control register by writing
Setting the bits in the Port A–D high drive enable subregisters to 1 configures, the
specified port pins for high output current drive operation. The Port A–D high drive
enable subregister affects the pins directly and, as a result, alternate functions are also
affected.
PHDE[7:0]—Port high drive enabled
0 = The port pin is configured for standard output current drive.
1 = The port pin is configured for high output current drive.
Port A–D Stop Mode Recovery Source Enable Subregisters
The Port A–D Stop Mode Recovery source enable subregister is accessed through the Port
A–D control register by writing
Setting the bits in the Port A–D Stop Mode Recovery source enable subregisters to1,
configures the specified port pins as a Stop Mode Recovery source. During STOP mode,
any logic transition on a port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
PSMRE6
PHDE6
R/W
R/W
6
0
6
0
PSMRE5
PHDE5
R/W
R/W
5
0
5
0
PSMRE4
04H
PHDE4
05H
R/W
R/W
4
0
4
0
to the Port A–D address register. See
to the Port A–D address register. See
PSMRE3
PHDE3
R/W
R/W
3
0
3
0
PSMRE2
PHDE2
R/W
R/W
Z8 Encore!
2
0
2
0
General Purpose Input/Output
Product Specification
PSMRE1
PHDE1
R/W
R/W
1
0
1
0
®
F083A Series
Table
Table
PSMRE0
21.
PHDE0
22.
R/W
R/W
0
0
0
0
47