Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 37

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Reset Sources
Table 9. Reset Sources and Resulting Reset Type
PS026308-1207
Operating Mode
NORMAL or HALT
modes
STOP mode
Power-On Reset
Table 9
Each device in the Z8 Encore! F083A Series contains an internal POR circuit. The POR
circuit monitors the digital supply voltage and holds the device in the Reset state until the
digital supply voltage reaches a safe operating level. After the supply voltage exceeds the
POR voltage threshold (V
has timed out. If the crystal oscillator is enabled by the option bits, the time-out is longer.
After the Z8 Encore! F083A Series device exits the POR state, the eZ8 CPU fetches the
reset vector. Following the POR, the POR status bit in the reset status (RSTSTAT) register
is set to 1.
Figure 6
Electrical Characteristics
Reset Source
Power-On Reset / Voltage
Brownout
WDT time-out
when configured for reset
RESET pin assertion
On-Chip Debugger initiated reset
(OCDCTL[0] set to 1)
Power-On Reset / Voltage
Brownout
RESET pin assertion
DBG pin driven Low
lists the possible sources of a system reset.
on page 26 displays POR operation. For POR threshold voltage (V
on page 177.
POR
), the device is held in the Reset state until the POR counter
Special Conditions
All reset pulses less than four system clocks in
All reset pulses less than 12 ns are ignored
Reset delay begins after supply voltage
exceeds POR level
None
width are ignored.
System, except the On-Chip Debugger is
unaffected by the reset
Reset delay begins after supply voltage
exceeds POR level
None
Z8 Encore!
Reset and Stop Mode Recovery
Product Specification
®
F083A Series
POR
), see
25