Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 45

IC ENCORE XP MCU FLASH 8K 28SOIC

Z8F083ASJ020EG

Manufacturer Part Number
Z8F083ASJ020EG
Description
IC ENCORE XP MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!®r
Datasheet

Specifications of Z8F083ASJ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Other names
269-4558-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F083ASJ020EG
Manufacturer:
Zilog
Quantity:
363
Low-Power Modes
STOP Mode
PS026308-1207
The Z8 Encore! F083A Series products contain power saving features. The highest level
of power reduction is provided by the STOP mode. The next level of power reduction is
provided by the HALT mode.
Further power savings are implemented by disabling the individual peripheral blocks
while in NORMAL mode.
You must not enable the pull-up register bits for unused GPIO pins, since these ports are
default output to VSS. Unused GPIOs include those missing on 20-pin packages, and the
ADC-enabled 28-pin packages.
Executing the eZ8 CPU’s STOP instruction places the device into STOP mode. In STOP
mode, the operating characteristics are:
To minimize the current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to VDD when the pull-up register bit is enabled or to one of power rail
(VDD or GND) when the pull-up register bit is disabled. The device is brought out of
STOP mode using Stop Mode Recovery. For more information about Stop Mode
Recovery, see
Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT (if
previously enabled) are disabled, and PA0/PA1 revert to the states programmed by the
GPIO registers.
System clock is stopped.
eZ8 CPU is stopped.
Program counter (PC) stops incrementing.
WDT’s internal RC oscillator continues to operate if enabled by the oscillator control
register.
If enabled, the WDT logic continues to operate.
If enabled for operation in STOP mode by the associated Flash option bit, the VBO
protection circuit continues to operate.
All other on-chip peripherals are idle.
Reset and Stop Mode Recovery
on page 23.
Z8 Encore!
Product Specification
®
Low-Power Modes
F083A Series
33

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