PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 111

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

TABLE 14-8:
14.6
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
Status register). This must be implemented in software.
Example 14-1 stores and restores the Status and W
registers. The user register, W_TEMP, must be defined
in a common memory location (i.e., W_TEMP is
defined at 0x70 in Bank 0 and is therefore, accessible
at 0xF0, 0x170 and 0x1F0). The Example 14-1:
• Stores the W register
• Stores the Status register
• Executes the ISR code
• Restores the Status (and bank select bit register)
• Restores the W register
EXAMPLE 14-1:
© 2009 Microchip Technology Inc.
10Bh, 18Bh
MOVWF
SWAPF
BCF
MOVWF
SWAPF
register
original
MOVWF
SWAPF
SWAPF
0Bh, 8Bh,
Address
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal
0Ch
8Ch
:
:(ISR)
:
Context Saving During Interrupts
W_TEMP
STATUS,W
STATUS,RP0 ;change to bank 0
STATUS_TEMP ;save status to bank 0
STATUS_TEMP,W;swap STATUS_TEMP
STATUS
W_TEMP,F
W_TEMP,W
operation.
INTCON
Name
PIR1
PIE1
SUMMARY OF INTERRUPT REGISTERS
SAVING THE STATUS
AND W REGISTERS IN
RAM
EEIF
EEIE
Bit 7
GIE
;copy W to temp register,
;could be in any bank
;swap status to be saved
;into W
;regardless of current
;bank
;register
;into W, sets bank to
;state
;move W into STATUS
;register
;swap W_TEMP
;swap W_TEMP into W
CMIE
CMIF
PEIE
Bit 6
RCIF
RCIE
Bit 5
T0IE
INTE
Bit 4
TXIF
TXIE
PIC16F627A/628A/648A
RBIE
Bit 3
—
—
14.7
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the CLKIN pin. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped, for example, by
execution of a SLEEP instruction. During normal
operation, a WDT time out generates a device Reset. If
the device is in Sleep mode, a WDT time out causes
the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by
programming the configuration bit WDTE as clear
(Section 14.1 “Configuration Bits”).
14.7.1
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, V
part (see DC Specifications, Table 17-7). If longer time-
out periods are desired, a postscaler with a division ratio
of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register. Thus,
time-out periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the Status register will be cleared upon a
Watchdog Timer time out.
14.7.2
It should also be taken in account that under worst case
conditions (V
WDT prescaler) it may take several seconds before a
WDT time out occurs.
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
Bit 2
T0IF
Watchdog Timer (WDT)
INTF
Bit 1
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
DD
DD
= Min., Temperature = Max., max.
and process variations from part to
RBIF
Bit 0
0000 000x
0000 -000
0000 -000
POR Reset
Value on
DS40044G-page 111
Value on all
0000 000u
0000 -000
0000 -000
Resets
other
(1)