PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 81

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

FIGURE 12-3:
TABLE 12-6:
© 2009 Microchip Technology Inc.
Legend:
Address
0Ch
8Ch
18h
19h
98h
99h
BRG output
(shift clock)
RB2/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Write to TXREG
Note:
SPBRG Baud Rate Generator Register
RCSTA
TXREG USART Transmit Data Register
TXSTA
Name
x = unknown, - = unimplemented locations read as ‘0’.
Shaded cells are not used for Asynchronous Transmission.
PIR1
PIE1
This timing diagram shows two consecutive transmissions.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
.
SPEN
CSRC
EEIE
Bit 7
EEIF
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Transmit Shift Reg.
Word 1
Word 1
CMIF
CMIE
Bit 6
RX9
TX9
Start bit
Word 2
SREN
TXEN
RCIF
RCIE
Bit 5
CREN
SYNC
Bit 4
TXIF
TXIE
bit 0
PIC16F627A/628A/648A
ADEN
Bit 3
—
—
—
bit 1
Word 1
CCP1IF
CCP1IE TMR2IE
BRGH
FERR
Bit 2
TMR2IF
OERR
TRMT
Bit 1
bit 7/8
Word 2
Transmit Shift Reg.
TMR1IF
TMR1IE
RX9D
TX9D
Bit 0
Stop bit
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
Value on
POR
Start bit
DS40044G-page 81
Word 2
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
Value on
all other
Resets
bit 0