PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 113

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.8.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the Status register
can be used to determine the cause of device Reset.
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT wake-up occurred.
FIGURE 14-17:
14.9
With the Code-Protect bit is cleared (Code-Protect
enabled), the contents of the program memory
locations are read out as ‘0’. See “PIC16F627A/628A/
648A EEPROM Memory Programming Specification”
(DS41196) for details.
© 2009 Microchip Technology Inc.
Note
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
Instruction
Fetched
Instruction
Executed
Note:
External Reset input on MCLR pin
Watchdog Timer wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB port change, or
any peripheral interrupt, which is active in Sleep.
1: XT, HS or LP Oscillator mode assumed.
2: T
3: GIE = 1 assumed. In this case, after wake-up the processor jumps to the interrupt routine. If GIE = 0, execution will continue
4: CLKOUT is not available in these Oscillator modes, but shown here for timing reference.
PC
(4)
Code Protection
in-line.
WAKE-UP FROM SLEEP
Only a Bulk Erase function can set the CP
and CPD bits by turning off the code
protection. The entire data EEPROM and
Flash program memory will be erased to
turn the code protection off.
OST
Inst(PC) = Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
= 1024 T
Inst(PC - 1)
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
(drawing not to scale). Approximately 1 μs delay will be there for RC Oscillator mode.
Inst(PC + 1)
Sleep
PC + 1
Processor in
Sleep
PC + 2
T
OST
(1,2)
PIC16F627A/628A/648A
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
(Note 2)
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have an NOP after the SLEEP
instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
14.10 User ID Locations
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store
checksum or other code-identification numbers. These
locations are not accessible during normal execution
but are readable and writable during Program/Verify.
Only the Least Significant 4 bits of the user ID locations
are used for checksum calculations although each
location has 14 bits.
PC + 2
Note:
Dummy cycle
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding
interrupt flag bits set, the device will not enter
Sleep. The SLEEP instruction is executed as
a NOP instruction.
PC + 2
Inst(0004h)
Dummy cycle
0004h
(3)
DS40044G-page 113
Inst(0005h)
Inst(0004h)
0005h