PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 85

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.3
12.3.1
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a
special provision for multiprocessor communication.
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA<3>) along with the RX9 bit. The
port is now programmed such that when the last bit is
received, the contents of the Receive Shift Register
(RSR) are transferred to the receive buffer, the ninth bit
of the RSR (RSR<8>) is transferred to RX9D, and the
receive interrupt is set if and only if RSR<8> = 1. This
feature can be used in a multiprocessor system as
follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a ‘1’
(instead of a ‘0’ for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling
multiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
When ADEN is enabled (= 1), all data bytes are
ignored. Following the Stop bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
TABLE 12-8:
© 2009 Microchip Technology Inc.
Legend:
Address
0Ch
1Ah
8Ch
18h
98h
99h
USART Address Detect Function
RCREG USART Receive Data Register
SPBRG Baud Rate Generator Register
RCSTA
TXSTA
USART 9-BIT RECEIVER WITH
ADDRESS DETECT
Name
PIR1
PIE1
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous
reception.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
CSRC
SPEN
EEIE
Bit 7
EEIF
CMIE
CMIF
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIF
Bit 5
CREN
SYNC
Bit 4
TXIF
TXIE
ADEN
Bit 3
PIC16F627A/628A/648A
—
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = 1). When ADEN is
disabled (= 0), all data bytes are received and the 9th
bit can be used as the parity bit.
The receive block diagram is shown in Figure 12-4.
Reception
(RCSTA<4>).
12.3.1.1
Follow these steps when setting up Asynchronous
Reception with Address Detect Enabled:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If an OERR error occurred, clear the error by
11. If the device has been addressed (RSR<8> = 1
BRGH
FERR
Bit 2
TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
Enable asynchronous communication by setting
or clearing bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
Set bit RX9 to enable 9-bit reception.
Set ADEN to enable address detect.
Enable the reception by setting enable bit CREN
or SREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
clearing enable bit CREN if it was already set.
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.
OERR
TRMT
Bit 1
is
Setting up 9-bit mode with Address
Detect
enabled
RX9D
TX9D
Bit 0
by
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
Value on
POR
setting
DS40044G-page 85
bit
Value on
all other
Resets
CREN