PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 46

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC16F627A/628A/648A
5.3
5.3.1
Any instruction that writes operates internally as a read
followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit 5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit 5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(e.g., bit 0) and is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the Input mode, no problem occurs. However,
if bit 0 is switched into Output mode later on, the
content of the data latch may now be unknown.
Reading a port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-2 shows the effect of two sequential read-
modify-write instructions (ex., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-OR”, “wired-
AND”). The resulting high output currents may damage
the chip.
FIGURE 5-16:
DS40044G-page 46
Note 1:
2:
Instruction
I/O Programming Considerations
BIDIRECTIONAL I/O PORTS
fetched
This example shows write to PORTB followed by a read from PORTB.
Data setup time = (0.25 T
to output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.
PC
Q1
SUCCESSIVE I/O OPERATION
MOVWF PORTB
Write to PORTB
Q2 Q3 Q4
PC
CY
- T
Q1
MOVF PORTB, W
PD
Read to PORTB
) where T
Execute
MOVWF
Q2 Q3 Q4
PORTB
PC + 1
T
CY
PD
= instruction cycle and T
EXAMPLE 5-2:
5.3.2
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-16). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction, which causes
that file to be read into the CPU, is executed. Other-
wise, the previous state of that pin may be read into
the CPU rather than the new state. When in doubt, it
is better to separate these instructions with a NOP or
another instruction not accessing this I/O port.
Q1
;Initial PORT settings:PORTB<7:4> Inputs
;
;PORTB<7:6> have external pull-up and are
;not connected to other circuitry
;
;
;
;Note that the user may have expected the
;pin values to be 00pp pppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(High).
BCF STATUS, RP0
BCF PORTB, 7
BSF STATUS, RP0
BCF TRISB, 7
BCF TRISB, 6
Port pin
sampled here
Q2 Q3 Q4 Q1
PC + 2
Execute
MOVF
PORTB, W
NOP
SUCCESSIVE OPERATIONS ON I/O
PORTS
PD
= propagation delay of Q1 cycle
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
© 2009 Microchip Technology Inc.
Q2 Q3 Q4
Execute
PC + 3
PORTB<3:0> Outputs
PORT latchPORT Pins
---------- ----------
;
;01pp pppp 11pp pppp
;
;10pp pppp 11pp pppp
;10pp pppp 10pp pppp
NOP
NOP