PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 177

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Q
Q-Clock ............................................................................... 61
Quick-Turnaround-Production (QTP) Devices ...................... 9
R
RC Oscillator ..................................................................... 101
RC Oscillator Mode
Reader Response ............................................................. 174
Registers
Reset................................................................................. 101
RETFIE Instruction............................................................ 126
RETLW Instruction ............................................................ 127
RETURN Instruction ......................................................... 127
Revision History ................................................................ 171
RLF Instruction.................................................................. 127
RRF Instruction ................................................................. 128
S
Serial Communication Interface (SCI) Module, See USART
Serialized Quick-Turnaround-Production (SQTP) Devices ... 9
SLEEP Instruction ............................................................. 128
Software Simulator (MPLAB SIM)..................................... 133
Special Event Trigger. See Compare
Special Features of the CPU .............................................. 97
Special Function Registers ................................................. 20
Status Register ................................................................... 24
SUBLW Instruction............................................................ 128
SUBWF Instruction ........................................................... 129
SWAPF Instruction............................................................ 129
T
T1CKPS0 bit ....................................................................... 50
T1CKPS1 bit ....................................................................... 50
T1CON Register ................................................................. 50
T1OSCEN bit ...................................................................... 50
T2CKPS0 bit ....................................................................... 55
T2CKPS1 bit ....................................................................... 55
T2CON Register ................................................................. 55
Timer0
Timer1
© 2009 Microchip Technology Inc.
Block Diagram........................................................... 101
CCP1CON (CCP Operation)....................................... 57
CMCON (Comparator Configuration).......................... 63
CONFIG (Configuration Word).................................... 98
EECON1 (EEPROM Control Register 1) .................... 92
INTCON (Interrupt Control)......................................... 26
Maps
OPTION_REG (Option) .............................................. 25
PCON (Power Control) ............................................... 29
PIE1 (Peripheral Interrupt Enable 1)........................... 27
PIR1 (Peripheral Interrupt Register 1) ........................ 28
Status.......................................................................... 24
T1CON Timer1 Control).............................................. 50
T2CON Timer2 Control).............................................. 55
Block Diagrams
External Clock Input.................................................... 47
Interrupt....................................................................... 47
Prescaler..................................................................... 48
Switching Prescaler Assignment................................. 49
Timer0 Module ............................................................ 47
Asynchronous Counter Mode ..................................... 52
Capacitor Selection..................................................... 53
PIC16F627A ................................................. 18, 19
PIC16F628A ................................................. 18, 19
Timer0/WDT ....................................................... 48
PIC16F627A/628A/648A
Timer2
Timing Diagrams
Timing Diagrams and Specifications ................................ 144
TMR0 Interrupt.................................................................. 110
TMR1CS bit ........................................................................ 50
TMR1ON bit........................................................................ 50
TMR2ON bit........................................................................ 55
TOUTPS0 bit ...................................................................... 55
TOUTPS1 bit ...................................................................... 55
TOUTPS2 bit ...................................................................... 55
TOUTPS3 bit ...................................................................... 55
TRIS Instruction ................................................................ 129
TRISA ................................................................................. 33
TRISB ................................................................................. 38
U
Universal Synchronous Asynchronous Receiver Transmitter
USART
External Clock Input ................................................... 51
External Clock Input Timing........................................ 52
Oscillator..................................................................... 53
Prescaler .............................................................. 51, 53
Resetting Timer1 ........................................................ 53
Resetting Timer1 Registers ........................................ 53
Special Event Trigger (CCP) ...................................... 59
Synchronized Counter Mode ...................................... 51
Timer Mode ................................................................ 51
TMR1H ....................................................................... 52
TMR1L........................................................................ 52
Block Diagram ............................................................ 54
Postscaler................................................................... 54
PR2 register................................................................ 54
Prescaler .............................................................. 54, 61
Timer2 Module............................................................ 54
TMR2 output ............................................................... 54
TMR2 to PR2 Match Interrupt..................................... 60
Timer0 ...................................................................... 147
Timer1 ...................................................................... 147
USART
USART Asynchronous Master Transmission ............. 80
USART Asynchronous Reception .............................. 83
USART Synchronous Reception ................................ 89
USART Synchronous Transmission ........................... 87
(USART) ..................................................................... 73
Asynchronous Receiver
Asynchronous Receiver Mode
Asynchronous Mode................................................... 79
Asynchronous Receiver.............................................. 82
Asynchronous Reception............................................ 84
Asynchronous Transmission ...................................... 80
Asynchronous Transmitter.......................................... 79
Baud Rate Generator (BRG) ...................................... 75
Block Diagrams
BRGH bit .................................................................... 75
Sampling......................................................... 76, 77, 78
Synchronous Master Mode......................................... 86
Synchronous Master Reception ................................. 88
Synchronous Master Transmission ............................ 86
Synchronous Slave Mode........................................... 89
Synchronous Slave Reception ................................... 90
Asynchronous Receiver...................................... 83
Setting Up Reception.......................................... 85
Address Detect ................................................... 85
Block Diagram .................................................... 85
Transmit.............................................................. 80
USART Receive ................................................. 82
DS40044G-page 177