PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 83

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

FIGURE 12-5:
FIGURE 12-6:
FIGURE 12-7:
© 2009 Microchip Technology Inc.
RB1/RX/DT (Pin)
RB1/RX/DT (pin)
RB1/RX/DT (pin)
RCV Shift Reg
RCV Shift Reg
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
RCIF
(interrupt flag)
ADEN = 1
(Address Match
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
ADEN = 1
(Address Match
RCV Shift
Reg
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
ADEN
(Address Match
Note:
Note:
Enable)
Enable)
Enable)
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and bit 8 = 0.
This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0.
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.
‘1’
‘1’
Start
Start
Start
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
bit
bit
bit
bit 0
bit 0
bit 0
bit 8 = 1, Address Byte
bit 8 = 1, Address Byte
bit 8 = 0, Data Byte
bit 1
bit 1
bit 1
bit 8
bit 8
bit 8
Stop
Stop
Stop
bit
bit
bit
Word 1
RCREG
Word 1
RCREG
PIC16F627A/628A/648A
Start
Start
Start
bit
bit
bit
bit 8 = 1, Address Byte
bit 0
bit 0
bit 0
bit 8 = 0, Data Byte
bit 8 = 0, Data Byte
bit 8
bit 8
bit 8
Stop
Stop
Stop
bit
bit
bit
Word 2
RCREG
Word 1
RCREG
DS40044G-page 83
‘1’
‘1’