AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 671
![IC MCU ARM9 217LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9260B-CU-999
Manufacturer Part Number
AT91SAM9260B-CU-999
Description
IC MCU ARM9 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9260B-CU-999.pdf
(798 pages)
Specifications of AT91SAM9260B-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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37.4.2
37.4.3
37.5
37.5.1
6221I–ATARM–17-Jul-09
Functional Description
Power Management
Interrupt
Host Controller Interface
The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a
correct accuracy of ± 0.25%.
Thus the USB device peripheral receives two clocks from the Power Management Controller
(PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the
UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain).
The USB host interface has an interrupt line connected to the Advanced Interrupt Controller
(AIC).
Handling USB host interrupts requires programming the AIC before configuring the UHP.
Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a.
There are two communication channels between the Host Controller and the Host Controller
Driver. The first channel uses a set of operational registers located on the USB Host Controller.
The Host Controller is the target for all communications on this channel. The operational regis-
ters contain control, status and list pointer registers. They are mapped in the memory mapped
area. Within the operational register set there is a pointer to a location in the processor address
space named the Host Controller Communication Area (HCCA). The HCCA is the second com-
munication channel. The host controller is the master for all communication on this channel. The
HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to
the done queue and status information associated with start-of-frame processing.
The basic building blocks for communication across the interface are Endpoint Descriptors (ED,
4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns
an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked
to the Endpoint Descriptor for the specific endpoint.
AT91SAM9260
671
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