AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 94

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

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AT91SAM9260
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best
accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but
may result in losing status events because the status register is cleared two Slow Clock cycles
after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow
Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the
interrupt must be disabled in the interrupt handler and re-enabled when the status register is
clear.
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time
Value Register). As this value can be updated asynchronously from the Master Clock, it is advis-
able to read this register twice at the same value to improve accuracy of the returned value.
The current value of the counter is compared with the value written in the alarm register
RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in
RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF,
after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit
can be used to start a periodic interrupt, the period being one second when the RTPRES is pro-
grammed with 0x8000 and Slow Clock equal to 32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the
new programmed value. This also resets the 32-bit counter.
Note:
Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):
1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2
slow clock cycles after the write of the RTTRST bit in the RTT_MR register.
2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the
RTT_SR (Status Register).
6221I–ATARM–17-Jul-09