AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 763

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

43.2.10
43.2.10.1
43.2.10.2
43.2.10.3
43.2.10.4
43.2.11
43.2.11.1
6221I–ATARM–17-Jul-09
Serial Peripheral Interface (SPI)
Serial Synchronous Controller (SSC)
Bad Serial Clock Generation on Second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
Baudrate Set to 1
SPI: PDC Data Loss
SPI: Software Reset Needs to be Written Twice
Unexpected RK Clock Cycle when RK Outputs a Clock During Data Transfer
If the SPI is used in the following configuration:
then an additional pulse will be generated on output PSCK during the second transfer.
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
When Baudrate is set to 1 (i.e., when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No error occurs if BITS field
equals 8,10,12,14 or 16 and Baudrate = 1.
None.
One byte data can be lost when PDC transmits. This occurs when write accesses are performed
on the base address of any peripheral, during the PDC transfer.
If a software reset (SWRST in the SPI Control Register) is performed, the SPI may not work
properly (the clock is enabled before the chip select).
The SPI Control Register field SWRST needs to be written twice to be correctly set.
When the SSC receiver is used in the following configuration:
• master mode
• CPOL = 1 and NCPHA = 0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• transmit with the slowest chip select and then with the fastest one
• Add a timeout for the PDC transfer and check the value of the PDC transmit counter when the
• Check the data integrity by a checksum.
• Avoid write access on the base address of peripherals during a PDC transfer.
• the internal clock divider is used (CKS = 0 and DIV different from 0),
• RK pin set as output and provides the clock during data transfer (CKO = 2)
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR not equal to 1
timeout has elapsed.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
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