P89LPC972FDH,129 NXP Semiconductors, P89LPC972FDH,129 Datasheet - Page 25

• Manufacturer Part Number: P89LPC972FDH,129
• Description: MCU 80C51 8KB FLASH 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC972FDH,129

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290299129

NXP Semiconductors
P89LPC97X
Product data sheet
7.16.1.1 Quasi-bidirectional output configuration
7.16.1.2 Open-drain output configuration
7.16.1 Port configurations
7.16 I/O ports
The P89LPC970/971/972 has four I/O ports: Port 0, Port 1 and Port 3. Ports 0, 1 are 8-bit
ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the
clock and reset options chosen, as shown in
Table 7.
All but three I/O port pins on the P89LPC970/971/972 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to V
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
Clock source
On-chip oscillator or watchdog
oscillator
External clock input
Low/medium/high speed
oscillator (external crystal or
resonator)
1. P1.5/RST can only be an input and cannot be configured.
2. P1.2/SCL/T0 and P1.3/INT0/SDA/T4 may only be configured to be either input-only or
open-drain.
DD
.
Number of I/O pins available
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2010
8-bit microcontroller with accelerated two-clock 80C51 core
Reset option
no external reset (except during
power-up)
external RST pin supported
no external reset (except during
power-up)
external RST pin supported
no external reset (except during
power-up)
external RST pin supported
Table
P89LPC970/971/972
7.
© NXP B.V. 2010. All rights reserved.
Number of I/O
pins (20-pin
package)
18
17
17
16
16
15
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