P89LPC972FDH,129 NXP Semiconductors, P89LPC972FDH,129 Datasheet - Page 41

• Manufacturer Part Number: P89LPC972FDH,129
• Description: MCU 80C51 8KB FLASH 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC972FDH,129

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290299129

NXP Semiconductors
P89LPC97X
Product data sheet
Fig 15. Watchdog timer in Watchdog mode (WDTE = 1)
oscillator
oscillator
400 kHz
25 kHz
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
(CLKCON.5)
sequence.
WDMOD
0
1
7.28.1 Software reset
7.28.2 Dual data pointers
7.29.1 General description
7.28 Additional features
7.29 Flash program memory
watchdog
oscillator
PCLK
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects one of
the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS
bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1
register, without the possibility of inadvertently altering other bits in the register.
The P89LPC970/971/972 flash memory provides in-circuit electrical erasure and
programming. The flash can be erased, read, and written as bytes. The Sector and Page
Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase
operation will erase the entire program memory. ICP using standard commercial
programmers is available. In addition, IAP and byte-erase allows code memory to be used
for non-volatile data storage. On-chip erase and write timing generation contribute to a
user-friendly programming interface. The P89LPC970/971/972 flash reliably stores
memory contents even after 100000 erase and program cycles. The cell is designed to
0
1
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
oscillator
crystal
(CLKCON.4)
XTALWD
0
1
WDCON (A7H)
All information provided in this document is subject to legal disclaimers.
÷32
Rev. 3 — 8 June 2010
8-bit microcontroller with accelerated two-clock 80C51 core
PRE2
PRESCALER
PRE1
PRE0
SHADOW REGISTER
P89LPC970/971/972
-
-
8-BIT DOWN
WDL (C1H)
COUNTER
WDRUN
WDTOF
© NXP B.V. 2010. All rights reserved.
WDCLK
reset
002aae542
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