P89LPC972FDH,129 NXP Semiconductors, P89LPC972FDH,129 Datasheet - Page 26

• Manufacturer Part Number: P89LPC972FDH,129
• Description: MCU 80C51 8KB FLASH 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC972FDH,129

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290299129

NXP Semiconductors
P89LPC97X
Product data sheet
7.16.1.3 Input-only configuration
7.16.1.4 Push-pull output configuration
7.16.2 Port 0 analog functions
7.16.3 Additional port features
7.16.4 Pin remap
The input-only port configuration has no output drivers. It is a Schmitt trigger input that
also has a glitch suppression circuit.
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a
Schmitt triggered input that also has a glitch suppression circuit. The P89LPC970/971/972
device has high current source on eight pins in push-pull mode. See
values”.
The P89LPC970/971/972 incorporates two Analog Comparators. In order to give the best
analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the input-only (high-impedance)
mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
After power-up, all pins are in input-only mode. Please note that this is different from
the LPC76x series of devices.
Every output on the P89LPC970/971/972 has been designed to sink typical LED drive
current. However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
This feature allows the functions of UART/I2C/SPI to be remapped to other pins.
Configuration register controls the multiplexers to allow connection between the pins and
the on chip peripherals. See
UART/I2C/SPI, each has two options of pin configuration: primary pin map and alternative
pin map. After reset, UART/I2C/SPI chooses the primary pin map as default. User can
adjust to the alternative pin map through configuring PINCON register according to the
application.
Please refer to P89LPC970/971/972 User manual for detail configurations.
•
•
After power-up, all I/O pins except P1.5, may be configured by software.
Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or
open-drain.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2010
8-bit microcontroller with accelerated two-clock 80C51 core
Table 11 “Static characteristics”
Table 8 “SPI/I2C/UART pin
P89LPC970/971/972
remap”.
for detailed specifications.
Table 10 “Limiting
© NXP B.V. 2010. All rights reserved.
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