P89LPC972FDH,129 NXP Semiconductors, P89LPC972FDH,129 Datasheet - Page 38

• Manufacturer Part Number: P89LPC972FDH,129
• Description: MCU 80C51 8KB FLASH 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC972FDH,129

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290299129

NXP Semiconductors
P89LPC97X
Product data sheet
7.25 Analog comparators
Two analog comparators are provided on the P89LPC970/971/972. Input and output
options allow use of the comparators in a number of different configurations. Comparator
operation is such that the output is a logical one (which may be read in a register and/or
routed to a pin) when the positive input (one of two selectable pins) is greater than the
negative input (selectable from a pin or an internal reference voltage). Otherwise the
output is a zero. Each comparator may be configured to cause an interrupt when the
output value changes.
The overall connections to both comparators are shown in
function to V
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 μs. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COn, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will
cause an interrupt if the comparator interrupt is enabled. The user should therefore
disable the comparator interrupt prior to disabling the comparator. Additionally, the user
should clear the comparator flag, CMFn, after disabling the comparator.
Fig 13. SPI single master multiple slaves configuration
GENERATOR
8-BIT SHIFT
SPI CLOCK
REGISTER
DD
master
= 2.4 V.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2010
8-bit microcontroller with accelerated two-clock 80C51 core
MISO
MOSI
SPICLK
port
port
P89LPC970/971/972
SPICLK
SPICLK
MISO
MOSI
MISO
MOSI
Figure
SS
SS
14. The comparators
8-BIT SHIFT
8-BIT SHIFT
REGISTER
REGISTER
© NXP B.V. 2010. All rights reserved.
slave
slave
002aaa903
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