MC56F8014VFAE Freescale Semiconductor, MC56F8014VFAE Datasheet - Page 83

• Manufacturer Part Number: MC56F8014VFAE
• Description: IC DIGITAL SIGNAL CTRLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8014VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Cpu Family: 56F8xxx
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 2(4-chx12-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO56F8014-E - BOARD DEMO MC56F8014 W/UNIV PSDEMO56F8014 - BOARD DEMO MC56F8014 W/US PSAPMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8014-EE - BOARD DEMO FOR 56F8014
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

memory chapter in MC56F8000RM, the 56F8000 Peripheral Reference Manual for details. When flash
security mode is enabled, the 56F8014 will disable the core EOnCE debug capabilities. Normal program
execution is otherwise unaffected.
7.2 Flash Access Lock and Unlock Mechanisms
There are several methods that effectively lock or unlock the on-chip flash.
7.2.1
On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE
port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active
and provides the chip’s boundary scan capability and access to the ID register, but proper implementation
of flash security will block any attempt to access the internal flash memory via the EOnCE port when
security is enabled.
7.2.2
If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash
contents, including the configuration field, thus disabling security (the protection register is cleared). This
does not compromise security, as the entire contents of the user’s secured code stored in flash are erased
before security is disabled on the device on the next reset or power-up sequence.
To
(LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register.
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock
divider value must be shifted into the corresponding 7-bit data register. After the data register has been
updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout
sequence to commence. The controller must remain in this state until the erase sequence has completed.
Refer to MC56F8000RM, the 56F8000 Peripheral Reference Manual, for more details, or contact
Freescale.
Note:
7.2.3
CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by
Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory configuration
file. The command Unlock_Flash_on_Connect1 in the .cfg file accomplishes the same task as using the
Debug menu.
This lockout recovery mechanism also includes the complete erasure of the internal flash contents,
including the configuration field, thus disabling security (the protection register is cleared).
7.2.4
The user can un-secure a secured device by programming the word $0000 into program memory location
$00 1FF7. After completing the programming, both the JTAG TAP controller and the device must be reset
Freescale Semiconductor
start
Disabling EOnCE Access
Flash Lockout Recovery Using JTAG
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
and the device to return to normal unsecured operation. Power-on reset will also reset both.
Flash Lockout Recovery Using CodeWarrior
Flash Lockout Recovery Without Mass Erase
the
lockout
recovery
56F8014 Technical Data, Rev. 11
sequence
via
JTAG,
the
Flash Access Lock and Unlock Mechanisms
JTAG
public
instruction
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