MC56F8014VFAE Freescale Semiconductor, MC56F8014VFAE Datasheet - Page 9

• Manufacturer Part Number: MC56F8014VFAE
• Description: IC DIGITAL SIGNAL CTRLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8014VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Cpu Family: 56F8xxx
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 2(4-chx12-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO56F8014-E - BOARD DEMO MC56F8014 W/UNIV PSDEMO56F8014 - BOARD DEMO MC56F8014 W/US PSAPMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8014-EE - BOARD DEMO FOR 56F8014
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

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1.4 Architecture Block Diagram
The 56F8014’s architecture is shown in
how the 56800E system buses communicate with internal memories and the IPBus Bridge, as well as
showing the internal connections between each unit of the 56800E core.
and control blocks connected to the IPBus Bridge.
The figures do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see
Descriptions
1.5 Synchronize ADC with PWM
ADC conversion can be synchronized with the PWM module via Quad Timer channel 2 and 3 if needed.
Internally, the PWM synch signal — which is generated at every PWM reload —can be connected to the
timer channel 3 input, and the timer channel 2 and channel 3 outputs are connected to the ADC sync inputs.
Timer channel 3 output is connected to SYNC0 and timer channel 2 is connected to SYNC1. The setting
is controlled by the TC3_INP bit in the SIM Control Register; see
SYNC0 is the master ADC sync input, used to trigger both ADCA and ADCB in sequence and parallel
mode. SYNC1 is used to trigger ADCB in parallel independent mode, while SYNC0 is used to trigger
ADCA. See MC56F8000RM, the 56F801X Peripheral Reference Manual, for additional information.
1.6 Multiple Frequency PWM Output
When both PWM channels of a complementary pair in software control mode and software control bits
are set to 1, each complementary PWM signal pair — PWM 0 and 1; PWM 2 and 3; and PWM 4 and 5 —
can select a PWM source from one of the following sources. This will enable each PWM pair and PWM2
to output PWM signals at different frequencies.
Freescale Semiconductor
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•
•
External GPIO input:
— GPIOB2 input can be used to drive PWM 0 and 1
— GPIOB3 input can be used to drive PWM 2
— GPIOB4 input can be used to drive PWM 4 and 5
Quad Timer output:
— Timer0 output can be used to drive PWM 0 and 1
— Timer2 output can be used to drive PWM 2
— Timer3 output can be used to drive PWM 4 and 5
ADC conversion result:
— Signal of over/under limit of ADC sample 0 can be used to drive PWM 0 and 1
— Signal of over/under limit of ADC sample 1 can be used to drive PWM 2
to see which signals are multiplexed with those of other peripherals.
56F8014 Technical Data, Rev. 11
Figure
1-1,
Figure 1-3
Figure
details how the device’s I/O pins are muxed.
1-2, and
Section
Figure
Figure 1-2
6.3.1.
Part 2 Signal/Connection
1-3.
Figure 1-1
shows the peripherals
Architecture Block Diagram
illustrates
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