MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 102

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Core Timer
10.2 Core Timer Status and Control Register
The read/write core timer status and control register (CTSCR) contains the interrupt flag bits, interrupt
enable bits, interrupt flag bit resets, and the rate selects for the real-time interrupt as shown in
CTOF — Core Timer Overflow Flag
RTIF — Real-Time Interrupt Flag
CTOFE — Core Timer Overflow Interrupt Enable Bit
RTIE — Real-Time Interrupt Enable Bit
CTOFR — Core Timer Overflow Flag Reset Bit
RTIFR — Real-Time Interrupt Flag Reset Bit
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
102
This read-only flag becomes set when the first eight stages of the core timer counter roll over from $FF
to $00. The CTOF flag bit generates a timer overflow interrupt request if CTOFE is also set. The CTOF
flag bit is cleared by writing a logic 1 to the CTOFR bit. Writing to CTOF has no effect. Reset clears
CTOF.
This read-only flag becomes set when the selected real-time interrupt (RTI) output becomes active.
RTIF generates a real-time interrupt request if RTIE is also set. The RTIF enable bit is cleared by
writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF.
This read/write bit enables core timer overflow interrupts. Reset clears CTOFE.
This read/write bit enables real-time interrupts. Reset clears RTIE.
Writing a logic 1 to this write-only bit clears the CTOF bit. CTOFR always reads as a logic 0. Reset
does not affect CTOFR.
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads as a logic 0. Reset does
not affect RTIFR.
These read/write bits select one of four real-time interrupt rates, as shown in
selected RTI output drives the COP watchdog, changing the real -time interrupt rate also changes the
1 = Overflow in core timer has occurred.
0 = No overflow of core timer since CTOF last cleared
1 = Overflow in real-time counter has occurred.
0 = No overflow of real-time counter since RTIF last cleared
1 = Core timer overflow interrupts enabled
0 = Core timer overflow interrupts disabled
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
1 = Clear CTOF flag bit
0 = No effect on CTOF flag bit
1 = Clear RTIF flag bit
0 = No effect on RTIF flag bit
Address:
Reset:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Figure 10-2. Core Timer Status and Control Register (CTSCR)
$0008
CTOF
Bit 7
0
= Unimplemented
RTIF
6
0
CTOFE
5
0
RTIE
4
0
CTOFR
3
0
0
RTIFR
2
0
0
RT1
1
1
Table
Freescale Semiconductor
10-1. Because the
Bit 0
RT0
1
Figure
10-2.