MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 135

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
RSP
RTI
RTS
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SEC
SEI
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SWI
Source
Form
Rotate Byte Right
through Carry Bit
Reset Stack Pointer
Return from Interrupt
Return from
Subroutine
Subtract Memory Byte
and Carry Bit from
Accumulator
Set Carry Bit
Set Interrupt Mask
Store Accumulator in
Memory
Stop Oscillator and
Enable IRQ Pin
Store Index
Register In Memory
Subtract Memory Byte
from
Accumulator
Software Interrupt
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Operation
Table 14-6. Instruction Set Summary (Sheet 5 of 6)
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (CCR)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← (SP) + 1; Pull (PCL)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) – 1; I ← 1
A ← (A) – (M) – (C)
b7
A ← (A) – (M)
SP ← $00FF
Description
M ← (A)
M ← (X)
C ← 1
I ← 1
b0
C
— —
— — — — —
— —
— — — — 1
— 1 — — —
— —
— 0 — — —
— —
— —
— 1 — — —
H
on CCR
I
Effect
N Z C
—
—
Þ
Instruction Set Summary
IMM
EXT
EXT
EXT
IMM
EXT
DIR
INH
INH
INH
INH
INH
DIR
INH
INH
DIR
INH
DIR
DIR
INH
IX1
IX2
IX1
IX2
IX1
IX2
IX1
IX2
IX1
IX
IX
IX
IX
IX
CF
DF
9C
A2
B2
C2
D2
E2
F2
9B
B7
C7
D7
E7
F7
8E
BF
EF
FF
A0
B0
C0
D0
E0
F0
36
46
56
66
76
80
99
83
ee ff
ee ff
ee ff
ee ff
hh ll
hh ll
hh ll
hh ll
dd
dd
dd
dd
dd
ff
ff
ff
ff
ff
ii
ii
10
5
3
3
6
5
2
6
2
3
4
5
4
3
2
2
4
5
6
5
4
2
4
5
6
5
4
2
3
4
5
4
3
135