MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 45

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.4.2 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error
detection system and must be cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to the COPC bit of the COPR register at location
$1FF0. The COPC bit, shown in
EPMSEC — EPROM Security
OPT — Optional Features Bit
COPC — COP Clear Bit
The COP watchdog reset will assert the pulldown device to pull the RESET pin low for three to four cycles
of the internal bus.
The COP watchdog reset function can be enabled or disabled by programming the COPEN bit in the
MOR.
5.4.3 Low-Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage on the V
the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low for three to four
cycles of the internal bus.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
Freescale Semiconductor
difficult for unauthorized users.
The EPMSEC bit is an EPROM, write-only security bit to protect the contents of the user EPROM code
stored in locations $0700–$1FFF.
The OPT bit enables two additional features: direct drive by comparator 1 output to PB4 and voltage
offset capability to sample capacitor in analog subsystem.
COPC is a write-only bit. Periodically writing a logic 0 to COPC prevents the COP watchdog from
resetting the MCU. Reset clears the COPC bit.
1 = Optional features enabled
0 = Optional features disabled
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
Address:
See
descriptions of the OPT bit.
Reset:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
8.7.1 Voltage Comparator 1
$1FF0
EPMSEC
Bit 7
U
Figure 5-2. COP and Security Register (COPR)
(1)
= Unimplemented
Figure
OPT
Bit
U
6
5-2, is a write-only bit.
U
5
and
NOTE
U = Unaffected
U
4
8.10 Sample and Hold
U
3
U
2
for further
U
1
DD
COPC
Bit 0
U
pin falls below
Internal Resets
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